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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
e6f5b35b JL |
2 | /* |
3 | * Copyright 2008 Freescale Semiconductor, Inc. | |
e6f5b35b JL |
4 | */ |
5 | ||
6 | #include <common.h> | |
e6f5b35b | 7 | |
5614e71b YS |
8 | #include <fsl_ddr_sdram.h> |
9 | #include <fsl_ddr_dimm_params.h> | |
e6f5b35b | 10 | |
dfb49108 HW |
11 | void fsl_ddr_board_options(memctl_options_t *popts, |
12 | dimm_params_t *pdimm, | |
13 | unsigned int ctrl_num) | |
e6f5b35b JL |
14 | { |
15 | /* | |
16 | * Factors to consider for clock adjust: | |
17 | * - number of chips on bus | |
18 | * - position of slot | |
19 | * - DDR1 vs. DDR2? | |
20 | * - ??? | |
21 | * | |
22 | * This needs to be determined on a board-by-board basis. | |
23 | * 0110 3/4 cycle late | |
24 | * 0111 7/8 cycle late | |
25 | */ | |
26 | popts->clk_adjust = 6; | |
27 | ||
28 | /* | |
29 | * Factors to consider for CPO: | |
30 | * - frequency | |
31 | * - ddr1 vs. ddr2 | |
32 | */ | |
33 | popts->cpo_override = 10; | |
34 | ||
35 | /* | |
36 | * Factors to consider for write data delay: | |
37 | * - number of DIMMs | |
38 | * | |
39 | * 1 = 1/4 clock delay | |
40 | * 2 = 1/2 clock delay | |
41 | * 3 = 3/4 clock delay | |
42 | * 4 = 1 clock delay | |
43 | * 5 = 5/4 clock delay | |
44 | * 6 = 3/2 clock delay | |
45 | */ | |
46 | popts->write_data_delay = 3; | |
47 | ||
48 | /* | |
49 | * Factors to consider for half-strength driver enable: | |
50 | * - number of DIMMs installed | |
51 | */ | |
52 | popts->half_strength_driver_enable = 0; | |
53 | } |