[thirdparty/u-boot.git] / board / freescale / mpc8568mds / law.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 */

#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>

/*
 * LAW(Local Access Window) configuration:
 *
 *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
 *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                512MB
 *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
 *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
 *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
 *4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M
 *5)   0xc000_0000   0xdfff_ffff     SRIO                    512MB
 *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
 *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
 *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
 *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
 *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
 *
 *Notes:
 *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 *    If flash is 8M at default position (last 8M), no LAW needed.
 *
 */

struct law_entry law_table[] = {
	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};

int num_law_entries = ARRAY_SIZE(law_table);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4d3521cc	2	/*
5f7bbd13	3	* Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
4d3521cc KG	4	*
	5	* (C) Copyright 2000
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4d3521cc KG	7	*/
	8
	9	#include <common.h>
	10	#include <asm/fsl_law.h>
	11	#include <asm/mmu.h>
	12
	13	/*
	14	* LAW(Local Access Window) configuration:
	15	*
	16	*0) 0x0000_0000 0x7fff_ffff DDR 2G
	17	*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
	18	*2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
	19	*-) 0xe000_0000 0xe00f_ffff CCSR 1M
	20	*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
	21	*4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
	22	*5) 0xc000_0000 0xdfff_ffff SRIO 512MB
	23	*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
	24	*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
	25	*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
	26	*6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
	27	*6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
	28	*
	29	*Notes:
	30	* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
	31	* If flash is 8M at default position (last 8M), no LAW needed.
	32	*
	33	*/
	34
	35	struct law_entry law_table[] = {
4d3521cc	36	/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
6d0f6bcf	37	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
4d3521cc KG	38	};
	39
	40	int num_law_entries = ARRAY_SIZE(law_table);