[people/ms/u-boot.git] / board / freescale / mpc8568mds / tlb.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 Initializations */
	/*
	 * TLBe 0:	16M	Non-cacheable, guarded
	 * 0xff000000	16M	FLASH (upper half)
	 * Out of reset this entry is only 4K.
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 0, BOOKE_PAGESZ_16M, 1),

	/*
	 * TLBe 1:	16M	Non-cacheable, guarded
	 * 0xfe000000	16M	FLASH (lower half)
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_16M, 1),

	/*
	 * TLBe 2:	1G	Non-cacheable, guarded
	 * 0x80000000	512M	PCI1 MEM
	 * 0xa0000000	512M	PCIe MEM
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 2, BOOKE_PAGESZ_1G, 1),

	/*
	 * TLBe 3:	64M	Non-cacheable, guarded
	 * 0xe000_0000	1M	CCSRBAR
	 * 0xe200_0000	8M	PCI1 IO
	 * 0xe280_0000	8M	PCIe IO
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLBe 4:	64M	Cacheable, non-guarded
	 * 0xf000_0000	64M	LBC SDRAM
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 4, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLBe 5:	256K	Non-cacheable, guarded
	 * 0xf8000000	32K BCSR
	 * 0xf8008000	32K PIB (CS4)
	 * 0xf8010000	32K PIB (CS5)
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_256K, 1),
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
73aa9ac2 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/mmu.h>
	28
	29	struct fsl_e_tlb_entry tlb_table[] = {
	30	/* TLB 0 - for temp stack in cache */
6d0f6bcf	31	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
73aa9ac2 KG	32	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
73aa9ac2 KG	33	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	34	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
73aa9ac2 KG	35	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
73aa9ac2 KG	36	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	37	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
73aa9ac2 KG	38	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
73aa9ac2 KG	39	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	40	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
73aa9ac2 KG	41	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	42	0, 0, BOOKE_PAGESZ_4K, 0),
	43
	44	/* TLB 1 Initializations */
	45	/*
	46	* TLBe 0: 16M Non-cacheable, guarded
	47	* 0xff000000 16M FLASH (upper half)
	48	* Out of reset this entry is only 4K.
	49	*/
6d0f6bcf	50	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
73aa9ac2 KG	51	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	52	0, 0, BOOKE_PAGESZ_16M, 1),
	53
	54	/*
	55	* TLBe 1: 16M Non-cacheable, guarded
	56	* 0xfe000000 16M FLASH (lower half)
	57	*/
6d0f6bcf	58	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
73aa9ac2 KG	59	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	60	0, 1, BOOKE_PAGESZ_16M, 1),
	61
	62	/*
	63	* TLBe 2: 1G Non-cacheable, guarded
	64	* 0x80000000 512M PCI1 MEM
53677ef1	65	* 0xa0000000 512M PCIe MEM
73aa9ac2	66	*/
6d0f6bcf	67	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
73aa9ac2 KG	68	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	69	0, 2, BOOKE_PAGESZ_1G, 1),
	70
	71	/*
	72	* TLBe 3: 64M Non-cacheable, guarded
	73	* 0xe000_0000 1M CCSRBAR
	74	* 0xe200_0000 8M PCI1 IO
	75	* 0xe280_0000 8M PCIe IO
	76	*/
6d0f6bcf	77	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
73aa9ac2 KG	78	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	79	0, 3, BOOKE_PAGESZ_64M, 1),
	80
	81	/*
	82	* TLBe 4: 64M Cacheable, non-guarded
	83	* 0xf000_0000 64M LBC SDRAM
	84	*/
6d0f6bcf	85	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
73aa9ac2 KG	86	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	87	0, 4, BOOKE_PAGESZ_64M, 1),
	88
	89	/*
	90	* TLBe 5: 256K Non-cacheable, guarded
	91	* 0xf8000000 32K BCSR
	92	* 0xf8008000 32K PIB (CS4)
	93	* 0xf8010000 32K PIB (CS5)
	94	*/
6d0f6bcf	95	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
73aa9ac2 KG	96	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	97	0, 5, BOOKE_PAGESZ_256K, 1),
	98	};
	99
	100	int num_tlb_entries = ARRAY_SIZE(tlb_table);