projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 765547dc HW |
1 | /* |
| 2 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | #include <common.h> | |
| 24 | #include <asm/io.h> | |
| 25 | ||
| 26 | #include "bcsr.h" | |
| 27 | ||
| 28 | void enable_8569mds_flash_write() | |
| 29 | { | |
| 16e7559c | 30 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); |
| 765547dc HW |
31 | } |
| 32 | ||
| 33 | void disable_8569mds_flash_write() | |
| 34 | { | |
| 35 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); | |
| 36 | } | |
| 37 | ||
| f82107f6 | 38 | void enable_8569mds_qe_uec() |
| 765547dc | 39 | { |
| f82107f6 | 40 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
| 765547dc HW |
41 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), |
| 42 | BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); | |
| 43 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), | |
| 44 | BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); | |
| 750098d3 HW |
45 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), |
| 46 | BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); | |
| 47 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), | |
| 48 | BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); | |
| f82107f6 HW |
49 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
| 50 | /* Set UCC1-4 working at RMII mode */ | |
| 51 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), | |
| 52 | BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); | |
| 53 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), | |
| 54 | BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); | |
| 55 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), | |
| 56 | BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); | |
| 57 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), | |
| 58 | BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); | |
| 59 | setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); | |
| 60 | #endif | |
| 765547dc HW |
61 | } |
| 62 | ||
| 63 | void disable_8569mds_brd_eeprom_write_protect() | |
| 64 | { | |
| 65 | clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); | |
| 66 | } |