[people/ms/u-boot.git] / board / freescale / mpc8572ds / mpc8572ds.c

/*
 * Copyright 2007-2008 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>

#include "../common/pixis.h"
#include "../common/sgmii_riser.h"

long int fixed_sdram(void);

int checkboard (void)
{
	printf ("Board: MPC8572DS, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
		in8(PIXIS_BASE + PIXIS_PVER));
	return 0;
}

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size = 0;

	puts("Initializing....");

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram();
#endif

	puts("    DDR: ");
	return dram_size;
}

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram (void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	uint d_init;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;

#if defined (CONFIG_DDR_ECC)
	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
}

#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);

int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
			devdisr, io_sel, host_agent);

	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		printf ("    eTSEC1 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
		printf ("    eTSEC2 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		printf ("    eTSEC3 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
		printf ("    eTSEC4 is in sgmii mode.\n");


#ifdef CONFIG_PCIE3
	{
		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
		struct pci_controller *hose = &pcie3_hose;
		int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
			(host_agent == 5) || (host_agent == 6);
		int pcie_configured  = io_sel >= 1;
		struct pci_region *r = hose->regions;
		u32 temp32;

		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
			printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
					pcie_ep ? "End Point" : "Root Complex",
					(uint)pci);
			if (pci->pme_msg_det) {
				pci->pme_msg_det = 0xffffffff;
				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
			}
			printf ("\n");

			/* inbound */
			r += fsl_pci_setup_inbound_windows(r);

			/* outbound memory */
			pci_set_region(r++,
					CONFIG_SYS_PCIE3_MEM_BASE,
					CONFIG_SYS_PCIE3_MEM_PHYS,
					CONFIG_SYS_PCIE3_MEM_SIZE,
					PCI_REGION_MEM);

			/* outbound io */
			pci_set_region(r++,
					CONFIG_SYS_PCIE3_IO_BASE,
					CONFIG_SYS_PCIE3_IO_PHYS,
					CONFIG_SYS_PCIE3_IO_SIZE,
					PCI_REGION_IO);

			hose->region_count = r - hose->regions;
			hose->first_busno=first_free_busno;
			pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

			fsl_pci_init(hose);

			first_free_busno=hose->last_busno+1;
			printf ("    PCIE3 on bus %02x - %02x\n",
					hose->first_busno,hose->last_busno);

			/*
			 * Activate ULI1575 legacy chip by performing a fake
			 * memory access.  Needed to make ULI RTC work.
			 * Device 1d has the first on-board memory BAR.
			 */

			pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
					PCI_BASE_ADDRESS_1, &temp32);
			if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
				debug(" uli1572 read to %x\n", temp32);
				in_be32((unsigned *)temp32);
			}
		} else {
			printf ("    PCIE3: disabled\n");
		}

	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE2
	{
		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
		struct pci_controller *hose = &pcie2_hose;
		int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
			(host_agent == 6) || (host_agent == 0);
		int pcie_configured  = io_sel & 4;
		struct pci_region *r = hose->regions;

		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
			printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
					pcie_ep ? "End Point" : "Root Complex",
					(uint)pci);
			if (pci->pme_msg_det) {
				pci->pme_msg_det = 0xffffffff;
				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
			}
			printf ("\n");

			/* inbound */
			r += fsl_pci_setup_inbound_windows(r);

			/* outbound memory */
			pci_set_region(r++,
					CONFIG_SYS_PCIE2_MEM_BASE,
					CONFIG_SYS_PCIE2_MEM_PHYS,
					CONFIG_SYS_PCIE2_MEM_SIZE,
					PCI_REGION_MEM);

			/* outbound io */
			pci_set_region(r++,
					CONFIG_SYS_PCIE2_IO_BASE,
					CONFIG_SYS_PCIE2_IO_PHYS,
					CONFIG_SYS_PCIE2_IO_SIZE,
					PCI_REGION_IO);

			hose->region_count = r - hose->regions;
			hose->first_busno=first_free_busno;
			pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

			fsl_pci_init(hose);
			first_free_busno=hose->last_busno+1;
			printf ("    PCIE2 on bus %02x - %02x\n",
					hose->first_busno,hose->last_busno);

		} else {
			printf ("    PCIE2: disabled\n");
		}

	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif
#ifdef CONFIG_PCIE1
	{
		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
		struct pci_controller *hose = &pcie1_hose;
		int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
			(host_agent == 5);
		int pcie_configured  = io_sel & 6;
		struct pci_region *r = hose->regions;

		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
			printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
					pcie_ep ? "End Point" : "Root Complex",
					(uint)pci);
			if (pci->pme_msg_det) {
				pci->pme_msg_det = 0xffffffff;
				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
			}
			printf ("\n");

			/* inbound */
			r += fsl_pci_setup_inbound_windows(r);

			/* outbound memory */
			pci_set_region(r++,
					CONFIG_SYS_PCIE1_MEM_BASE,
					CONFIG_SYS_PCIE1_MEM_PHYS,
					CONFIG_SYS_PCIE1_MEM_SIZE,
					PCI_REGION_MEM);

			/* outbound io */
			pci_set_region(r++,
					CONFIG_SYS_PCIE1_IO_BASE,
					CONFIG_SYS_PCIE1_IO_PHYS,
					CONFIG_SYS_PCIE1_IO_SIZE,
					PCI_REGION_IO);

			hose->region_count = r - hose->regions;
			hose->first_busno=first_free_busno;

			pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

			fsl_pci_init(hose);

			first_free_busno=hose->last_busno+1;
			printf("    PCIE1 on bus %02x - %02x\n",
					hose->first_busno,hose->last_busno);

		} else {
			printf ("    PCIE1: disabled\n");
		}

	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif
}
#endif

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = 2;

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash + promjet */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, flashbase,		/* tlb, epn, rpn */
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */

	return 0;
}

#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char ics307_S_to_OD[] = {
	10, 2, 8, 4, 5, 7, 3, 6
};

/* Calculate frequency being generated by ICS307-02 clock chip based upon
 * the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	unsigned long RDW = cw2 & 0x7F;
	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	unsigned long freq;

	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */

	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
	 *
	 * R6:R0 = Reference Divider Word (RDW)
	 * V8:V0 = VCO Divider Word (VDW)
	 * S2:S0 = Output Divider Select (OD)
	 * F1:F0 = Function of CLK2 Output
	 * TTL = duty cycle
	 * C1:C0 = internal load capacitance for cyrstal
	 */

	/* Adding 1 to get a "nicely" rounded number, but this needs
	 * more tweaking to get a "properly" rounded number. */

	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));

	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
			freq);
	return freq;
}

unsigned long get_board_sys_clk(ulong dummy)
{
	return ics307_clk_freq (
			in8(PIXIS_BASE + PIXIS_VSYSCLK0),
			in8(PIXIS_BASE + PIXIS_VSYSCLK1),
			in8(PIXIS_BASE + PIXIS_VSYSCLK2)
			);
}

unsigned long get_board_ddr_clk(ulong dummy)
{
	return ics307_clk_freq (
			in8(PIXIS_BASE + PIXIS_VDDRCLK0),
			in8(PIXIS_BASE + PIXIS_VDDRCLK1),
			in8(PIXIS_BASE + PIXIS_VDDRCLK2)
			);
}
#else
unsigned long get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;

	i = in8(PIXIS_BASE + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
		case 0:
			val = 33333333;
			break;
		case 1:
			val = 40000000;
			break;
		case 2:
			val = 50000000;
			break;
		case 3:
			val = 66666666;
			break;
		case 4:
			val = 83333333;
			break;
		case 5:
			val = 100000000;
			break;
		case 6:
			val = 133333333;
			break;
		case 7:
			val = 166666666;
			break;
	}

	return val;
}

unsigned long get_board_ddr_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;

	i = in8(PIXIS_BASE + PIXIS_SPD);
	i &= 0x38;
	i >>= 3;

	switch (i) {
		case 0:
			val = 33333333;
			break;
		case 1:
			val = 40000000;
			break;
		case 2:
			val = 50000000;
			break;
		case 3:
			val = 66666666;
			break;
		case 4:
			val = 83333333;
			break;
		case 5:
			val = 100000000;
			break;
		case 6:
			val = 133333333;
			break;
		case 7:
			val = 166666666;
			break;
	}
	return val;
}
#endif

#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct tsec_info_struct tsec_info[4];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC4
	SET_STD_TSEC_INFO(tsec_info[num], 4);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	fsl_sgmii_riser_init(tsec_info, num);

	tsec_eth_init(bis, tsec_info, num);

	return 0;
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
			struct pci_controller *hose);

void ft_board_setup(void *blob, bd_t *bd)
{
	ulong base, size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCIE3
	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
}
#endif

#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);

void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
129ba616 KG	1	/*
	2	* Copyright 2007-2008 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/mmu.h>
7c0d4a75	28	#include <asm/cache.h>
129ba616 KG	29	#include <asm/immap_85xx.h>
	30	#include <asm/immap_fsl_pci.h>
	31	#include <asm/fsl_ddr_sdram.h>
	32	#include <asm/io.h>
	33	#include <miiphy.h>
	34	#include <libfdt.h>
	35	#include <fdt_support.h>
7e183cad	36	#include <tsec.h>
129ba616 KG	37
129ba616 KG	38	#include "../common/pixis.h"
7e183cad	39	#include "../common/sgmii_riser.h"
129ba616	40
129ba616 KG	41	long int fixed_sdram(void);
	42
	43	int checkboard (void)
	44	{
	45	printf ("Board: MPC8572DS, System ID: 0x%02x, "
	46	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
	47	in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
	48	in8(PIXIS_BASE + PIXIS_PVER));
	49	return 0;
	50	}
	51
	52	phys_size_t initdram(int board_type)
	53	{
	54	phys_size_t dram_size = 0;
	55
	56	puts("Initializing....");
	57
	58	#ifdef CONFIG_SPD_EEPROM
	59	dram_size = fsl_ddr_sdram();
	60
	61	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	62
	63	dram_size *= 0x100000;
	64	#else
	65	dram_size = fixed_sdram();
	66	#endif
	67
129ba616 KG	68	puts(" DDR: ");
	69	return dram_size;
	70	}
	71
	72	#if !defined(CONFIG_SPD_EEPROM)
	73	/*
	74	* Fixed sdram init -- doesn't use serial presence detect.
	75	*/
	76
	77	phys_size_t fixed_sdram (void)
	78	{
6d0f6bcf	79	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
129ba616 KG	80	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	81	uint d_init;
	82
6d0f6bcf JCPV	83	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	84	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
129ba616	85
6d0f6bcf JCPV	86	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	87	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	88	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	89	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	90	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	91	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	92	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	93	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	94	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	95	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
129ba616 KG	96
129ba616 KG	97	#if defined (CONFIG_DDR_ECC)
6d0f6bcf JCPV	98	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	99	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	100	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
129ba616 KG	101	#endif
	102	asm("sync;isync");
	103
	104	udelay(500);
	105
6d0f6bcf	106	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
129ba616 KG	107
	108	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	109	d_init = 1;
	110	debug("DDR - 1st controller: memory initializing\n");
	111	/*
	112	* Poll until memory is initialized.
	113	* 512 Meg at 400 might hit this 200 times or so.
	114	*/
	115	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	116	udelay(1000);
	117	}
	118	debug("DDR: memory initialized\n\n");
	119	asm("sync; isync");
	120	udelay(500);
	121	#endif
	122
	123	return 512 * 1024 * 1024;
	124	}
	125
	126	#endif
	127
	128	#ifdef CONFIG_PCIE1
	129	static struct pci_controller pcie1_hose;
	130	#endif
	131
	132	#ifdef CONFIG_PCIE2
	133	static struct pci_controller pcie2_hose;
	134	#endif
	135
	136	#ifdef CONFIG_PCIE3
	137	static struct pci_controller pcie3_hose;
	138	#endif
	139
2dba0dea KG	140	extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
	141	extern void fsl_pci_init(struct pci_controller *hose);
	142
129ba616 KG	143	int first_free_busno=0;
	144	#ifdef CONFIG_PCI
	145	void pci_init_board(void)
	146	{
6d0f6bcf	147	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
129ba616 KG	148	uint devdisr = gur->devdisr;
	149	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	150	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	151
	152	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	153	devdisr, io_sel, host_agent);
	154
	155	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	156	printf (" eTSEC1 is in sgmii mode.\n");
	157	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	158	printf (" eTSEC2 is in sgmii mode.\n");
	159	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	160	printf (" eTSEC3 is in sgmii mode.\n");
	161	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
	162	printf (" eTSEC4 is in sgmii mode.\n");
	163
	164
	165	#ifdef CONFIG_PCIE3
	166	{
6d0f6bcf	167	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE3_ADDR;
129ba616 KG	168	struct pci_controller *hose = &pcie3_hose;
	169	int pcie_ep = (host_agent == 0) \|\| (host_agent == 3) \|\|
	170	(host_agent == 5) \|\| (host_agent == 6);
	171	int pcie_configured = io_sel >= 1;
2dba0dea	172	struct pci_region *r = hose->regions;
129ba616 KG	173	u32 temp32;
	174
	175	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	176	printf ("\n PCIE3 connected to ULI as %s (base address %x)",
	177	pcie_ep ? "End Point" : "Root Complex",
	178	(uint)pci);
	179	if (pci->pme_msg_det) {
	180	pci->pme_msg_det = 0xffffffff;
	181	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	182	}
	183	printf ("\n");
	184
	185	/* inbound */
2dba0dea	186	r += fsl_pci_setup_inbound_windows(r);
129ba616 KG	187
129ba616 KG	188	/* outbound memory */
2dba0dea	189	pci_set_region(r++,
6d0f6bcf JCPV	190	CONFIG_SYS_PCIE3_MEM_BASE,
	191	CONFIG_SYS_PCIE3_MEM_PHYS,
	192	CONFIG_SYS_PCIE3_MEM_SIZE,
129ba616 KG	193	PCI_REGION_MEM);
	194
	195	/* outbound io */
2dba0dea	196	pci_set_region(r++,
6d0f6bcf JCPV	197	CONFIG_SYS_PCIE3_IO_BASE,
	198	CONFIG_SYS_PCIE3_IO_PHYS,
	199	CONFIG_SYS_PCIE3_IO_SIZE,
129ba616 KG	200	PCI_REGION_IO);
129ba616 KG	201
2dba0dea	202	hose->region_count = r - hose->regions;
129ba616 KG	203	hose->first_busno=first_free_busno;
	204	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	205
	206	fsl_pci_init(hose);
	207
	208	first_free_busno=hose->last_busno+1;
	209	printf (" PCIE3 on bus %02x - %02x\n",
	210	hose->first_busno,hose->last_busno);
	211
	212	/*
	213	* Activate ULI1575 legacy chip by performing a fake
	214	* memory access. Needed to make ULI RTC work.
	215	* Device 1d has the first on-board memory BAR.
	216	*/
	217
	218	pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
	219	PCI_BASE_ADDRESS_1, &temp32);
6d0f6bcf	220	if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
129ba616 KG	221	debug(" uli1572 read to %x\n", temp32);
	222	in_be32((unsigned *)temp32);
	223	}
	224	} else {
	225	printf (" PCIE3: disabled\n");
	226	}
	227
	228	}
	229	#else
	230	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
	231	#endif
	232
	233	#ifdef CONFIG_PCIE2
	234	{
6d0f6bcf	235	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
129ba616 KG	236	struct pci_controller *hose = &pcie2_hose;
129ba616 KG	237	int pcie_ep = (host_agent == 2) \|\| (host_agent == 4) \|\|
86be510f	238	(host_agent == 6) \|\| (host_agent == 0);
129ba616	239	int pcie_configured = io_sel & 4;
2dba0dea	240	struct pci_region *r = hose->regions;
129ba616 KG	241
	242	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	243	printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
	244	pcie_ep ? "End Point" : "Root Complex",
	245	(uint)pci);
	246	if (pci->pme_msg_det) {
	247	pci->pme_msg_det = 0xffffffff;
	248	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	249	}
	250	printf ("\n");
	251
	252	/* inbound */
2dba0dea	253	r += fsl_pci_setup_inbound_windows(r);
129ba616 KG	254
129ba616 KG	255	/* outbound memory */
2dba0dea	256	pci_set_region(r++,
6d0f6bcf JCPV	257	CONFIG_SYS_PCIE2_MEM_BASE,
	258	CONFIG_SYS_PCIE2_MEM_PHYS,
	259	CONFIG_SYS_PCIE2_MEM_SIZE,
129ba616 KG	260	PCI_REGION_MEM);
	261
	262	/* outbound io */
2dba0dea	263	pci_set_region(r++,
6d0f6bcf JCPV	264	CONFIG_SYS_PCIE2_IO_BASE,
	265	CONFIG_SYS_PCIE2_IO_PHYS,
	266	CONFIG_SYS_PCIE2_IO_SIZE,
129ba616 KG	267	PCI_REGION_IO);
129ba616 KG	268
2dba0dea	269	hose->region_count = r - hose->regions;
129ba616 KG	270	hose->first_busno=first_free_busno;
	271	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	272
	273	fsl_pci_init(hose);
	274	first_free_busno=hose->last_busno+1;
	275	printf (" PCIE2 on bus %02x - %02x\n",
	276	hose->first_busno,hose->last_busno);
	277
	278	} else {
	279	printf (" PCIE2: disabled\n");
	280	}
	281
	282	}
	283	#else
	284	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
	285	#endif
	286	#ifdef CONFIG_PCIE1
	287	{
6d0f6bcf	288	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
129ba616	289	struct pci_controller *hose = &pcie1_hose;
86be510f	290	int pcie_ep = (host_agent <= 1) \|\| (host_agent == 4) \|\|
129ba616 KG	291	(host_agent == 5);
129ba616 KG	292	int pcie_configured = io_sel & 6;
2dba0dea	293	struct pci_region *r = hose->regions;
129ba616 KG	294
	295	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	296	printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
	297	pcie_ep ? "End Point" : "Root Complex",
	298	(uint)pci);
	299	if (pci->pme_msg_det) {
	300	pci->pme_msg_det = 0xffffffff;
	301	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	302	}
	303	printf ("\n");
	304
	305	/* inbound */
2dba0dea	306	r += fsl_pci_setup_inbound_windows(r);
129ba616 KG	307
129ba616 KG	308	/* outbound memory */
2dba0dea	309	pci_set_region(r++,
6d0f6bcf JCPV	310	CONFIG_SYS_PCIE1_MEM_BASE,
	311	CONFIG_SYS_PCIE1_MEM_PHYS,
	312	CONFIG_SYS_PCIE1_MEM_SIZE,
129ba616 KG	313	PCI_REGION_MEM);
	314
	315	/* outbound io */
2dba0dea	316	pci_set_region(r++,
6d0f6bcf JCPV	317	CONFIG_SYS_PCIE1_IO_BASE,
	318	CONFIG_SYS_PCIE1_IO_PHYS,
	319	CONFIG_SYS_PCIE1_IO_SIZE,
129ba616 KG	320	PCI_REGION_IO);
129ba616 KG	321
2dba0dea	322	hose->region_count = r - hose->regions;
129ba616 KG	323	hose->first_busno=first_free_busno;
	324
	325	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	326
	327	fsl_pci_init(hose);
	328
	329	first_free_busno=hose->last_busno+1;
	330	printf(" PCIE1 on bus %02x - %02x\n",
	331	hose->first_busno,hose->last_busno);
	332
	333	} else {
	334	printf (" PCIE1: disabled\n");
	335	}
	336
	337	}
	338	#else
	339	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	340	#endif
	341	}
	342	#endif
	343
	344	int board_early_init_r(void)
	345	{
6d0f6bcf	346	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
129ba616 KG	347	const u8 flash_esel = 2;
	348
	349	/*
	350	* Remap Boot flash + PROMJET region to caching-inhibited
	351	* so that flash can be erased properly.
	352	*/
	353
7c0d4a75	354	/* Flush d-cache and invalidate i-cache of any FLASH data */
3cbd8231 WD	355	flush_dcache();
3cbd8231 WD	356	invalidate_icache();
129ba616 KG	357
	358	/* invalidate existing TLB entry for flash + promjet */
	359	disable_tlb(flash_esel);
	360
	361	set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
	362	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	363	0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
	364
	365	return 0;
	366	}
	367
	368	#ifdef CONFIG_GET_CLK_FROM_ICS307
	369	/* decode S[0-2] to Output Divider (OD) */
	370	static unsigned char ics307_S_to_OD[] = {
	371	10, 2, 8, 4, 5, 7, 3, 6
	372	};
	373
	374	/* Calculate frequency being generated by ICS307-02 clock chip based upon
	375	* the control bytes being programmed into it. */
	376	/* XXX: This function should probably go into a common library */
	377	static unsigned long
	378	ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
	379	{
	380	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	381	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	382	unsigned long RDW = cw2 & 0x7F;
	383	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	384	unsigned long freq;
	385
	386	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
	387
	388	/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
	389	* cw1: V8 V7 V6 V5 V4 V3 V2 V1
	390	* cw2: V0 R6 R5 R4 R3 R2 R1 R0
	391	*
	392	* R6:R0 = Reference Divider Word (RDW)
	393	* V8:V0 = VCO Divider Word (VDW)
	394	* S2:S0 = Output Divider Select (OD)
	395	* F1:F0 = Function of CLK2 Output
	396	* TTL = duty cycle
	397	* C1:C0 = internal load capacitance for cyrstal
	398	*/
	399
	400	/* Adding 1 to get a "nicely" rounded number, but this needs
	401	* more tweaking to get a "properly" rounded number. */
	402
	403	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
	404
	405	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
	406	freq);
	407	return freq;
	408	}
	409
	410	unsigned long get_board_sys_clk(ulong dummy)
	411	{
	412	return ics307_clk_freq (
	413	in8(PIXIS_BASE + PIXIS_VSYSCLK0),
	414	in8(PIXIS_BASE + PIXIS_VSYSCLK1),
	415	in8(PIXIS_BASE + PIXIS_VSYSCLK2)
	416	);
	417	}
	418
	419	unsigned long get_board_ddr_clk(ulong dummy)
	420	{
421	return ics307_clk_freq (
422	in8(PIXIS_BASE + PIXIS_VDDRCLK0),
423	in8(PIXIS_BASE + PIXIS_VDDRCLK1),
424	in8(PIXIS_BASE + PIXIS_VDDRCLK2)
425	);
426	}
427	#else
428	unsigned long get_board_sys_clk(ulong dummy)
429	{
430	u8 i;
431	ulong val = 0;
432
433	i = in8(PIXIS_BASE + PIXIS_SPD);
434	i &= 0x07;
435
436	switch (i) {
437	case 0:
438	val = 33333333;
439	break;
440	case 1:
441	val = 40000000;
442	break;
443	case 2:
444	val = 50000000;
445	break;
446	case 3:
447	val = 66666666;
448	break;
449	case 4:
450	val = 83333333;
451	break;
452	case 5:
453	val = 100000000;
454	break;
455	case 6:
456	val = 133333333;
457	break;
458	case 7:
459	val = 166666666;
460	break;
461	}
462
463	return val;
464	}
465
466	unsigned long get_board_ddr_clk(ulong dummy)
467	{
468	u8 i;
469	ulong val = 0;
470
471	i = in8(PIXIS_BASE + PIXIS_SPD);
472	i &= 0x38;
473	i >>= 3;
474
475	switch (i) {
476	case 0:
477	val = 33333333;
478	break;
479	case 1:
480	val = 40000000;
481	break;
482	case 2:
483	val = 50000000;
484	break;
485	case 3:
486	val = 66666666;
487	break;
488	case 4:
489	val = 83333333;
490	break;
491	case 5:
492	val = 100000000;
493	break;
494	case 6:
495	val = 133333333;
496	break;
497	case 7:
498	val = 166666666;
499	break;
500	}
501	return val;
502	}
503	#endif
504
7e183cad LY	505	#ifdef CONFIG_TSEC_ENET
	506	int board_eth_init(bd_t *bis)
	507	{
	508	struct tsec_info_struct tsec_info[4];
	509	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	510	int num = 0;
	511
	512	#ifdef CONFIG_TSEC1
	513	SET_STD_TSEC_INFO(tsec_info[num], 1);
	514	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	515	tsec_info[num].flags \|= TSEC_SGMII;
	516	num++;
	517	#endif
	518	#ifdef CONFIG_TSEC2
	519	SET_STD_TSEC_INFO(tsec_info[num], 2);
	520	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	521	tsec_info[num].flags \|= TSEC_SGMII;
	522	num++;
	523	#endif
	524	#ifdef CONFIG_TSEC3
	525	SET_STD_TSEC_INFO(tsec_info[num], 3);
	526	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	527	tsec_info[num].flags \|= TSEC_SGMII;
	528	num++;
	529	#endif
	530	#ifdef CONFIG_TSEC4
	531	SET_STD_TSEC_INFO(tsec_info[num], 4);
	532	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
	533	tsec_info[num].flags \|= TSEC_SGMII;
	534	num++;
	535	#endif
	536
	537	if (!num) {
	538	printf("No TSECs initialized\n");
	539
	540	return 0;
	541	}
	542
	543	fsl_sgmii_riser_init(tsec_info, num);
	544
	545	tsec_eth_init(bis, tsec_info, num);
	546
	547	return 0;
	548	}
	549	#endif
	550
129ba616	551	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	552	extern void ft_fsl_pci_setup(void blob, const char pci_alias,
3cbd8231	553	struct pci_controller *hose);
2dba0dea	554
129ba616 KG	555	void ft_board_setup(void blob, bd_t bd)
129ba616 KG	556	{
129ba616 KG	557	ulong base, size;
	558
	559	ft_cpu_setup(blob, bd);
	560
	561	base = getenv_bootm_low();
	562	size = getenv_bootm_size();
	563
	564	fdt_fixup_memory(blob, (u64)base, (u64)size);
	565
129ba616	566	#ifdef CONFIG_PCIE3
2dba0dea	567	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
129ba616 KG	568	#endif
129ba616 KG	569	#ifdef CONFIG_PCIE2
2dba0dea	570	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
129ba616 KG	571	#endif
129ba616 KG	572	#ifdef CONFIG_PCIE1
2dba0dea	573	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
129ba616	574	#endif
129ba616 KG	575	}
	576	#endif
	577
	578	#ifdef CONFIG_MP
	579	extern void cpu_mp_lmb_reserve(struct lmb *lmb);
	580
	581	void board_lmb_reserve(struct lmb *lmb)
	582	{
	583	cpu_mp_lmb_reserve(lmb);
	584	}
	585	#endif