[people/ms/u-boot.git] / board / freescale / mpc8610hpcd / mpc8610hpcd.c

/*
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <i2c.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <netdev.h>

#include "../common/pixis.h"

void sdram_init(void);
phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);


/* called before any console output */
int board_early_init_f(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_gur_t *gur = &immap->im_gur;

	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */

	return 0;
}

int misc_init_r(void)
{
	u8 tmp_val, version;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	/*Do not use 8259PIC*/
	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);

	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
	version = in_8(pixis_base + PIXIS_PVER);
	if(version >= 0x07) {
		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
	}

	/* Using this for DIU init before the driver in linux takes over
	 *  Enable the TFP410 Encoder (I2C address 0x38)
	 */

	tmp_val = 0xBF;
	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);

	tmp_val = 0x10;
	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);

#ifdef CONFIG_FSL_DIU_FB
	mpc8610hpcd_diu_init();
#endif

	return 0;
}

int checkboard(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	mcm->abcr |= 0x00010000; /* 0 */
	mcm->hpmr3 = 0x80000008; /* 4c */
	mcm->hpmr0 = 0;
	mcm->hpmr1 = 0;
	mcm->hpmr2 = 0;
	mcm->hpmr4 = 0;
	mcm->hpmr5 = 0;

	return 0;
}


phys_size_t
initdram(int board_type)
{
	phys_size_t dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();
#endif

#if defined(CONFIG_SYS_RAMBOOT)
	puts(" DDR: ");
	return dram_size;
#endif

	puts(" DDR: ");
	return dram_size;
}


#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
	uint d_init;

	ddr->cs0_bnds = 0x0000001f;
	ddr->cs0_config = 0x80010202;

	ddr->timing_cfg_3 = 0x00000000;
	ddr->timing_cfg_0 = 0x00260802;
	ddr->timing_cfg_1 = 0x3935d322;
	ddr->timing_cfg_2 = 0x14904cc8;
	ddr->sdram_mode = 0x00480432;
	ddr->sdram_mode_2 = 0x00000000;
	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
	ddr->sdram_data_init = 0xDEADBEEF;
	ddr->sdram_clk_cntl = 0x03800000;
	ddr->sdram_cfg_2 = 0x04400010;

#if defined(CONFIG_DDR_ECC)
	ddr->err_int_en = 0x0000000d;
	ddr->err_disable = 0x00000000;
	ddr->err_sbe = 0x00010000;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/


#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
		udelay(1000);

	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}

#endif

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				 PCI_ENET0_MEMADDR,
				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
	{}
};
#endif


static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

int first_free_busno = 0;

void pci_init_board(void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
		>> MPC8610_PORDEVSR_IO_SEL_SHIFT;
	uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
		>> MPC8610_PORBMSR_HA_SHIFT;

	printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
		devdisr, io_sel, host_agent);

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
		printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det)
			pci->pme_msg_det = 0xffffffff;

		/* outbound memory */
		pci_set_region(r++,
			 CONFIG_SYS_PCIE1_MEM_BUS,
			 CONFIG_SYS_PCIE1_MEM_PHYS,
			 CONFIG_SYS_PCIE1_MEM_SIZE,
			 PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			 CONFIG_SYS_PCIE1_IO_BUS,
			 CONFIG_SYS_PCIE1_IO_PHYS,
			 CONFIG_SYS_PCIE1_IO_SIZE,
			 PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno = first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno = hose->last_busno + 1;
		printf(" PCI-Express 1 on bus %02x - %02x\n",
			hose->first_busno, hose->last_busno);

	} else
		puts(" PCI-Express 1: Disabled\n");
 }
#else
	puts("PCI-Express 1: Disabled\n");
#endif /* CONFIG_PCIE1 */


#ifdef CONFIG_PCIE2
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
	struct pci_controller *hose = &pcie2_hose;
	struct pci_region *r = hose->regions;

	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);

	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
		printf(" PCI-Express 2 connected to slot as %s" \
			" (base address %x)\n",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det)
			pci->pme_msg_det = 0xffffffff;

		/* outbound memory */
		pci_set_region(r++,
			 CONFIG_SYS_PCIE2_MEM_BUS,
			 CONFIG_SYS_PCIE2_MEM_PHYS,
			 CONFIG_SYS_PCIE2_MEM_SIZE,
			 PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			 CONFIG_SYS_PCIE2_IO_BUS,
			 CONFIG_SYS_PCIE2_IO_PHYS,
			 CONFIG_SYS_PCIE2_IO_SIZE,
			 PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno = first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno = hose->last_busno + 1;
		printf(" PCI-Express 2 on bus %02x - %02x\n",
			hose->first_busno, hose->last_busno);
	} else
		puts(" PCI-Express 2: Disabled\n");
 }
#else
	puts("PCI-Express 2: Disabled\n");
#endif /* CONFIG_PCIE2 */


#ifdef CONFIG_PCI1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
	struct pci_region *r = hose->regions;

	if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
		printf(" PCI connected to PCI slots as %s" \
			" (base address %x)\n",
			pci_agent ? "Agent" : "Host",
			(uint)pci);

		/* outbound memory */
		pci_set_region(r++,
			 CONFIG_SYS_PCI1_MEM_BUS,
			 CONFIG_SYS_PCI1_MEM_PHYS,
			 CONFIG_SYS_PCI1_MEM_SIZE,
			 PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			 CONFIG_SYS_PCI1_IO_BUS,
			 CONFIG_SYS_PCI1_IO_PHYS,
			 CONFIG_SYS_PCI1_IO_SIZE,
			 PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno = first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno = hose->last_busno + 1;
		printf(" PCI on bus %02x - %02x\n",
			hose->first_busno, hose->last_busno);


	} else
		puts(" PCI: Disabled\n");
 }
#endif /* CONFIG_PCI1 */
}

#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
			     "timebase-frequency", bd->bi_busfreq / 4, 1);
	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
			     "bus-frequency", bd->bi_busfreq, 1);
	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
			     "clock-frequency", bd->bi_intfreq, 1);
	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
			     "bus-frequency", bd->bi_busfreq, 1);

	do_fixup_by_compat_u32(blob, "ns16550",
			       "clock-frequency", bd->bi_busfreq, 1);

	fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);

#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
#endif
}
#endif

/*
 * get_board_sys_clk
 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 */

unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	i = in_8(pixis_base + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333000;
		break;
	case 1:
		val = 39999600;
		break;
	case 2:
		val = 49999500;
		break;
	case 3:
		val = 66666000;
		break;
	case 4:
		val = 83332500;
		break;
	case 5:
		val = 99999000;
		break;
	case 6:
		val = 133332000;
		break;
	case 7:
		val = 166665000;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}

void board_reset(void)
{
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	out_8(pixis_base + PIXIS_RST, 0);

	while (1)
		;
}
Commit	Line	Data
3dd2db53 JL	1	/*
	2	* Copyright 2007 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
c9974ab0	22
3dd2db53 JL	23	#include <common.h>
	24	#include <command.h>
	25	#include <pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/immap_86xx.h>
c8514622	28	#include <asm/fsl_pci.h>
39aa1a73	29	#include <asm/fsl_ddr_sdram.h>
c9974ab0	30	#include <i2c.h>
3dd2db53	31	#include <asm/io.h>
1df170f8 JL	32	#include <libfdt.h>
1df170f8 JL	33	#include <fdt_support.h>
a30a549a	34	#include <spd_sdram.h>
89973f8a	35	#include <netdev.h>
3dd2db53 JL	36
	37	#include "../common/pixis.h"
	38
3dd2db53	39	void sdram_init(void);
4c77de3f	40	phys_size_t fixed_sdram(void);
c9974ab0 JL	41	void mpc8610hpcd_diu_init(void);
c9974ab0 JL	42
3dd2db53 JL	43
	44	/* called before any console output */
	45	int board_early_init_f(void)
	46	{
6d0f6bcf	47	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53 JL	48	volatile ccsr_gur_t *gur = &immap->im_gur;
3dd2db53 JL	49
a877880c YS	50	gur->gpiocr \|= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
	51
	52	return 0;
	53	}
	54
	55	int misc_init_r(void)
	56	{
	57	u8 tmp_val, version;
048e7efe	58	u8 pixis_base = (u8 )PIXIS_BASE;
a877880c YS	59
a877880c YS	60	/Do not use 8259PIC/
048e7efe KG	61	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
048e7efe KG	62	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val \| 0x80);
a877880c YS	63
a877880c YS	64	/For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt/
048e7efe	65	version = in_8(pixis_base + PIXIS_PVER);
a877880c	66	if(version >= 0x07) {
048e7efe KG	67	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
048e7efe KG	68	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
a877880c YS	69	}
	70
	71	/* Using this for DIU init before the driver in linux takes over
	72	* Enable the TFP410 Encoder (I2C address 0x38)
	73	*/
	74
	75	tmp_val = 0xBF;
	76	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	77	/* Verify if enabled */
	78	tmp_val = 0;
	79	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	80	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
	81
	82	tmp_val = 0x10;
	83	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	84	/* Verify if enabled */
	85	tmp_val = 0;
	86	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	87	debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
	88
	89	#ifdef CONFIG_FSL_DIU_FB
	90	mpc8610hpcd_diu_init();
	91	#endif
3dd2db53 JL	92
	93	return 0;
	94	}
	95
	96	int checkboard(void)
	97	{
6d0f6bcf	98	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53	99	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
048e7efe	100	u8 pixis_base = (u8 )PIXIS_BASE;
3dd2db53	101
9b55a253 WD	102	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
9b55a253 WD	103	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
048e7efe KG	104	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
048e7efe KG	105	in_8(pixis_base + PIXIS_PVER));
3dd2db53 JL	106
	107	mcm->abcr \|= 0x00010000; /* 0 */
	108	mcm->hpmr3 = 0x80000008; /* 4c */
	109	mcm->hpmr0 = 0;
	110	mcm->hpmr1 = 0;
	111	mcm->hpmr2 = 0;
	112	mcm->hpmr4 = 0;
	113	mcm->hpmr5 = 0;
	114
	115	return 0;
	116	}
	117
	118
9973e3c6	119	phys_size_t
3dd2db53 JL	120	initdram(int board_type)
3dd2db53 JL	121	{
4c77de3f	122	phys_size_t dram_size = 0;
3dd2db53 JL	123
3dd2db53 JL	124	#if defined(CONFIG_SPD_EEPROM)
39aa1a73	125	dram_size = fsl_ddr_sdram();
3dd2db53 JL	126	#else
	127	dram_size = fixed_sdram();
	128	#endif
	129
6d0f6bcf	130	#if defined(CONFIG_SYS_RAMBOOT)
3dd2db53 JL	131	puts(" DDR: ");
	132	return dram_size;
	133	#endif
	134
3dd2db53 JL	135	puts(" DDR: ");
	136	return dram_size;
	137	}
	138
	139
3dd2db53 JL	140	#if !defined(CONFIG_SPD_EEPROM)
	141	/*
	142	* Fixed sdram init -- doesn't use serial presence detect.
	143	*/
	144
4c77de3f	145	phys_size_t fixed_sdram(void)
3dd2db53	146	{
6d0f6bcf JCPV	147	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	148	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53 JL	149	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
	150	uint d_init;
	151
	152	ddr->cs0_bnds = 0x0000001f;
	153	ddr->cs0_config = 0x80010202;
	154
45239cf4	155	ddr->timing_cfg_3 = 0x00000000;
3dd2db53 JL	156	ddr->timing_cfg_0 = 0x00260802;
	157	ddr->timing_cfg_1 = 0x3935d322;
	158	ddr->timing_cfg_2 = 0x14904cc8;
e7ee23ec	159	ddr->sdram_mode = 0x00480432;
3dd2db53 JL	160	ddr->sdram_mode_2 = 0x00000000;
	161	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
	162	ddr->sdram_data_init = 0xDEADBEEF;
	163	ddr->sdram_clk_cntl = 0x03800000;
	164	ddr->sdram_cfg_2 = 0x04400010;
	165
	166	#if defined(CONFIG_DDR_ECC)
	167	ddr->err_int_en = 0x0000000d;
	168	ddr->err_disable = 0x00000000;
	169	ddr->err_sbe = 0x00010000;
	170	#endif
	171	asm("sync;isync");
	172
	173	udelay(500);
	174
e7ee23ec	175	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
3dd2db53 JL	176
	177
	178	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	179	d_init = 1;
	180	debug("DDR - 1st controller: memory initializing\n");
	181	/*
	182	* Poll until memory is initialized.
	183	* 512 Meg at 400 might hit this 200 times or so.
	184	*/
	185	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
	186	udelay(1000);
	187
	188	debug("DDR: memory initialized\n\n");
	189	asm("sync; isync");
	190	udelay(500);
	191	#endif
	192
	193	return 512 * 1024 * 1024;
	194	#endif
6d0f6bcf	195	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
3dd2db53 JL	196	}
	197
	198	#endif
	199
	200	#if defined(CONFIG_PCI)
	201	/*
	202	* Initialize PCI Devices, report devices found.
	203	*/
	204
	205	#ifndef CONFIG_PCI_PNP
	206	static struct pci_config_table pci_fsl86xxads_config_table[] = {
	207	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	208	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	209	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	210	PCI_ENET0_MEMADDR,
	211	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER} },
	212	{}
	213	};
	214	#endif
	215
	216
	217	static struct pci_controller pci1_hose = {
	218	#ifndef CONFIG_PCI_PNP
	219	config_table:pci_mpc86xxcts_config_table
	220	#endif
	221	};
	222	#endif /* CONFIG_PCI */
	223
	224	#ifdef CONFIG_PCIE1
	225	static struct pci_controller pcie1_hose;
	226	#endif
	227
	228	#ifdef CONFIG_PCIE2
	229	static struct pci_controller pcie2_hose;
	230	#endif
	231
	232	int first_free_busno = 0;
	233
	234	void pci_init_board(void)
	235	{
6d0f6bcf	236	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
3dd2db53 JL	237	volatile ccsr_gur_t *gur = &immap->im_gur;
3dd2db53 JL	238	uint devdisr = gur->devdisr;
a551cee9 JL	239	uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
	240	>> MPC8610_PORDEVSR_IO_SEL_SHIFT;
	241	uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
	242	>> MPC8610_PORBMSR_HA_SHIFT;
3dd2db53 JL	243
	244	printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	245	devdisr, io_sel, host_agent);
	246
3dd2db53 JL	247	#ifdef CONFIG_PCIE1
3dd2db53 JL	248	{
6d0f6bcf	249	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
3dd2db53	250	struct pci_controller *hose = &pcie1_hose;
865f24dc KG	251	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
865f24dc KG	252	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
c2083e0e	253	struct pci_region *r = hose->regions;
3dd2db53 JL	254
	255	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
	256	printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
	257	pcie_ep ? "End Point" : "Root Complex",
	258	(uint)pci);
	259	if (pci->pme_msg_det)
	260	pci->pme_msg_det = 0xffffffff;
	261
3dd2db53	262	/* outbound memory */
c2083e0e	263	pci_set_region(r++,
3e3fffe3	264	CONFIG_SYS_PCIE1_MEM_BUS,
6d0f6bcf JCPV	265	CONFIG_SYS_PCIE1_MEM_PHYS,
6d0f6bcf JCPV	266	CONFIG_SYS_PCIE1_MEM_SIZE,
3dd2db53 JL	267	PCI_REGION_MEM);
	268
	269	/* outbound io */
c2083e0e	270	pci_set_region(r++,
3e3fffe3	271	CONFIG_SYS_PCIE1_IO_BUS,
6d0f6bcf JCPV	272	CONFIG_SYS_PCIE1_IO_PHYS,
6d0f6bcf JCPV	273	CONFIG_SYS_PCIE1_IO_SIZE,
3dd2db53 JL	274	PCI_REGION_IO);
3dd2db53 JL	275
c2083e0e	276	hose->region_count = r - hose->regions;
3dd2db53 JL	277
3dd2db53 JL	278	hose->first_busno = first_free_busno;
3dd2db53	279
fb3143b3	280	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
3dd2db53 JL	281
	282	first_free_busno = hose->last_busno + 1;
	283	printf(" PCI-Express 1 on bus %02x - %02x\n",
	284	hose->first_busno, hose->last_busno);
	285
	286	} else
	287	puts(" PCI-Express 1: Disabled\n");
	288	}
	289	#else
	290	puts("PCI-Express 1: Disabled\n");
	291	#endif /* CONFIG_PCIE1 */
	292
	293
	294	#ifdef CONFIG_PCIE2
	295	{
6d0f6bcf	296	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
3dd2db53	297	struct pci_controller *hose = &pcie2_hose;
c2083e0e	298	struct pci_region *r = hose->regions;
3dd2db53	299
865f24dc KG	300	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
865f24dc KG	301	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
3dd2db53 JL	302
	303	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
	304	printf(" PCI-Express 2 connected to slot as %s" \
	305	" (base address %x)\n",
	306	pcie_ep ? "End Point" : "Root Complex",
	307	(uint)pci);
	308	if (pci->pme_msg_det)
	309	pci->pme_msg_det = 0xffffffff;
	310
3dd2db53	311	/* outbound memory */
c2083e0e	312	pci_set_region(r++,
3e3fffe3	313	CONFIG_SYS_PCIE2_MEM_BUS,
6d0f6bcf JCPV	314	CONFIG_SYS_PCIE2_MEM_PHYS,
6d0f6bcf JCPV	315	CONFIG_SYS_PCIE2_MEM_SIZE,
3dd2db53 JL	316	PCI_REGION_MEM);
	317
	318	/* outbound io */
c2083e0e	319	pci_set_region(r++,
3e3fffe3	320	CONFIG_SYS_PCIE2_IO_BUS,
6d0f6bcf JCPV	321	CONFIG_SYS_PCIE2_IO_PHYS,
6d0f6bcf JCPV	322	CONFIG_SYS_PCIE2_IO_SIZE,
3dd2db53 JL	323	PCI_REGION_IO);
3dd2db53 JL	324
c2083e0e	325	hose->region_count = r - hose->regions;
3dd2db53 JL	326
3dd2db53 JL	327	hose->first_busno = first_free_busno;
3dd2db53	328
fb3143b3	329	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
3dd2db53 JL	330
	331	first_free_busno = hose->last_busno + 1;
	332	printf(" PCI-Express 2 on bus %02x - %02x\n",
	333	hose->first_busno, hose->last_busno);
	334	} else
	335	puts(" PCI-Express 2: Disabled\n");
	336	}
	337	#else
	338	puts("PCI-Express 2: Disabled\n");
	339	#endif /* CONFIG_PCIE2 */
	340
	341
	342	#ifdef CONFIG_PCI1
	343	{
6d0f6bcf	344	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
3dd2db53	345	struct pci_controller *hose = &pci1_hose;
865f24dc	346	int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
c2083e0e	347	struct pci_region *r = hose->regions;
3dd2db53 JL	348
	349	if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
	350	printf(" PCI connected to PCI slots as %s" \
	351	" (base address %x)\n",
	352	pci_agent ? "Agent" : "Host",
	353	(uint)pci);
	354
3dd2db53	355	/* outbound memory */
c2083e0e	356	pci_set_region(r++,
3e3fffe3	357	CONFIG_SYS_PCI1_MEM_BUS,
6d0f6bcf JCPV	358	CONFIG_SYS_PCI1_MEM_PHYS,
6d0f6bcf JCPV	359	CONFIG_SYS_PCI1_MEM_SIZE,
3dd2db53 JL	360	PCI_REGION_MEM);
	361
	362	/* outbound io */
c2083e0e	363	pci_set_region(r++,
3e3fffe3	364	CONFIG_SYS_PCI1_IO_BUS,
6d0f6bcf JCPV	365	CONFIG_SYS_PCI1_IO_PHYS,
6d0f6bcf JCPV	366	CONFIG_SYS_PCI1_IO_SIZE,
3dd2db53 JL	367	PCI_REGION_IO);
3dd2db53 JL	368
c2083e0e	369	hose->region_count = r - hose->regions;
3dd2db53 JL	370
3dd2db53 JL	371	hose->first_busno = first_free_busno;
3dd2db53	372
fb3143b3	373	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
3dd2db53 JL	374
	375	first_free_busno = hose->last_busno + 1;
	376	printf(" PCI on bus %02x - %02x\n",
	377	hose->first_busno, hose->last_busno);
	378
	379
	380	} else
	381	puts(" PCI: Disabled\n");
	382	}
	383	#endif /* CONFIG_PCI1 */
	384	}
	385
1df170f8	386	#if defined(CONFIG_OF_BOARD_SETUP)
3dd2db53 JL	387	void
	388	ft_board_setup(void blob, bd_t bd)
	389	{
1df170f8 JL	390	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
	391	"timebase-frequency", bd->bi_busfreq / 4, 1);
	392	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
	393	"bus-frequency", bd->bi_busfreq, 1);
	394	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
	395	"clock-frequency", bd->bi_intfreq, 1);
	396	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
	397	"bus-frequency", bd->bi_busfreq, 1);
3dd2db53	398
1df170f8 JL	399	do_fixup_by_compat_u32(blob, "ns16550",
	400	"clock-frequency", bd->bi_busfreq, 1);
	401
	402	fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
	403
3dd2db53	404	#ifdef CONFIG_PCI1
c2083e0e	405	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
3dd2db53 JL	406	#endif
3dd2db53 JL	407	#ifdef CONFIG_PCIE1
c2083e0e	408	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
3dd2db53 JL	409	#endif
3dd2db53 JL	410	#ifdef CONFIG_PCIE2
c2083e0e	411	ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
3dd2db53	412	#endif
3dd2db53 JL	413	}
	414	#endif
	415
	416	/*
	417	* get_board_sys_clk
	418	* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
	419	*/
	420
	421	unsigned long
	422	get_board_sys_clk(ulong dummy)
	423	{
a877880c	424	u8 i;
3dd2db53	425	ulong val = 0;
048e7efe	426	u8 pixis_base = (u8 )PIXIS_BASE;
3dd2db53	427
048e7efe	428	i = in_8(pixis_base + PIXIS_SPD);
3dd2db53 JL	429	i &= 0x07;
	430
	431	switch (i) {
	432	case 0:
	433	val = 33333000;
	434	break;
	435	case 1:
	436	val = 39999600;
	437	break;
	438	case 2:
	439	val = 49999500;
	440	break;
	441	case 3:
	442	val = 66666000;
	443	break;
	444	case 4:
	445	val = 83332500;
	446	break;
	447	case 5:
	448	val = 99999000;
	449	break;
	450	case 6:
	451	val = 133332000;
	452	break;
	453	case 7:
	454	val = 166665000;
	455	break;
	456	}
	457
	458	return val;
	459	}
65d3d99c	460
65d3d99c BW	461	int board_eth_init(bd_t *bis)
65d3d99c BW	462	{
89973f8a	463	return pci_eth_init(bis);
65d3d99c	464	}
4ef630df PT	465
	466	void board_reset(void)
	467	{
048e7efe KG	468	u8 pixis_base = (u8 )PIXIS_BASE;
	469
	470	out_8(pixis_base + PIXIS_RST, 0);
4ef630df PT	471
	472	while (1)
	473	;
	474	}