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3dd2db53 JL |
1 | /* |
2 | * Copyright 2007 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
c9974ab0 | 22 | |
3dd2db53 JL |
23 | #include <common.h> |
24 | #include <command.h> | |
25 | #include <pci.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/immap_86xx.h> | |
28 | #include <asm/immap_fsl_pci.h> | |
c9974ab0 | 29 | #include <i2c.h> |
3dd2db53 | 30 | #include <asm/io.h> |
1df170f8 JL |
31 | #include <libfdt.h> |
32 | #include <fdt_support.h> | |
a30a549a | 33 | #include <spd_sdram.h> |
3dd2db53 JL |
34 | |
35 | #include "../common/pixis.h" | |
36 | ||
37 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
38 | extern void ddr_enable_ecc(unsigned int dram_size); | |
39 | #endif | |
40 | ||
3dd2db53 JL |
41 | void sdram_init(void); |
42 | long int fixed_sdram(void); | |
c9974ab0 JL |
43 | void mpc8610hpcd_diu_init(void); |
44 | ||
3dd2db53 JL |
45 | |
46 | /* called before any console output */ | |
47 | int board_early_init_f(void) | |
48 | { | |
49 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
50 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
51 | ||
a877880c YS |
52 | gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | int misc_init_r(void) | |
58 | { | |
59 | u8 tmp_val, version; | |
60 | ||
61 | /*Do not use 8259PIC*/ | |
62 | tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); | |
63 | out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); | |
64 | ||
65 | /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ | |
66 | version = in8(PIXIS_BASE + PIXIS_PVER); | |
67 | if(version >= 0x07) { | |
68 | tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); | |
69 | out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); | |
70 | } | |
71 | ||
72 | /* Using this for DIU init before the driver in linux takes over | |
73 | * Enable the TFP410 Encoder (I2C address 0x38) | |
74 | */ | |
75 | ||
76 | tmp_val = 0xBF; | |
77 | i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); | |
78 | /* Verify if enabled */ | |
79 | tmp_val = 0; | |
80 | i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); | |
81 | debug("DVI Encoder Read: 0x%02lx\n",tmp_val); | |
82 | ||
83 | tmp_val = 0x10; | |
84 | i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); | |
85 | /* Verify if enabled */ | |
86 | tmp_val = 0; | |
87 | i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); | |
88 | debug("DVI Encoder Read: 0x%02lx\n",tmp_val); | |
89 | ||
90 | #ifdef CONFIG_FSL_DIU_FB | |
91 | mpc8610hpcd_diu_init(); | |
92 | #endif | |
3dd2db53 JL |
93 | |
94 | return 0; | |
95 | } | |
96 | ||
97 | int checkboard(void) | |
98 | { | |
99 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
3dd2db53 JL |
100 | volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; |
101 | ||
102 | puts("Board: MPC8610HPCD\n"); | |
103 | ||
104 | mcm->abcr |= 0x00010000; /* 0 */ | |
105 | mcm->hpmr3 = 0x80000008; /* 4c */ | |
106 | mcm->hpmr0 = 0; | |
107 | mcm->hpmr1 = 0; | |
108 | mcm->hpmr2 = 0; | |
109 | mcm->hpmr4 = 0; | |
110 | mcm->hpmr5 = 0; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | ||
9973e3c6 | 116 | phys_size_t |
3dd2db53 JL |
117 | initdram(int board_type) |
118 | { | |
119 | long dram_size = 0; | |
120 | ||
121 | #if defined(CONFIG_SPD_EEPROM) | |
122 | dram_size = spd_sdram(); | |
123 | #else | |
124 | dram_size = fixed_sdram(); | |
125 | #endif | |
126 | ||
127 | #if defined(CFG_RAMBOOT) | |
128 | puts(" DDR: "); | |
129 | return dram_size; | |
130 | #endif | |
131 | ||
132 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
133 | /* | |
134 | * Initialize and enable DDR ECC. | |
135 | */ | |
136 | ddr_enable_ecc(dram_size); | |
137 | #endif | |
138 | ||
139 | puts(" DDR: "); | |
140 | return dram_size; | |
141 | } | |
142 | ||
143 | ||
3dd2db53 JL |
144 | #if !defined(CONFIG_SPD_EEPROM) |
145 | /* | |
146 | * Fixed sdram init -- doesn't use serial presence detect. | |
147 | */ | |
148 | ||
149 | long int fixed_sdram(void) | |
150 | { | |
151 | #if !defined(CFG_RAMBOOT) | |
152 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
153 | volatile ccsr_ddr_t *ddr = &immap->im_ddr1; | |
154 | uint d_init; | |
155 | ||
156 | ddr->cs0_bnds = 0x0000001f; | |
157 | ddr->cs0_config = 0x80010202; | |
158 | ||
45239cf4 | 159 | ddr->timing_cfg_3 = 0x00000000; |
3dd2db53 JL |
160 | ddr->timing_cfg_0 = 0x00260802; |
161 | ddr->timing_cfg_1 = 0x3935d322; | |
162 | ddr->timing_cfg_2 = 0x14904cc8; | |
163 | ddr->sdram_mode_1 = 0x00480432; | |
164 | ddr->sdram_mode_2 = 0x00000000; | |
165 | ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ | |
166 | ddr->sdram_data_init = 0xDEADBEEF; | |
167 | ddr->sdram_clk_cntl = 0x03800000; | |
168 | ddr->sdram_cfg_2 = 0x04400010; | |
169 | ||
170 | #if defined(CONFIG_DDR_ECC) | |
171 | ddr->err_int_en = 0x0000000d; | |
172 | ddr->err_disable = 0x00000000; | |
173 | ddr->err_sbe = 0x00010000; | |
174 | #endif | |
175 | asm("sync;isync"); | |
176 | ||
177 | udelay(500); | |
178 | ||
179 | ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ | |
180 | ||
181 | ||
182 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
183 | d_init = 1; | |
184 | debug("DDR - 1st controller: memory initializing\n"); | |
185 | /* | |
186 | * Poll until memory is initialized. | |
187 | * 512 Meg at 400 might hit this 200 times or so. | |
188 | */ | |
189 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) | |
190 | udelay(1000); | |
191 | ||
192 | debug("DDR: memory initialized\n\n"); | |
193 | asm("sync; isync"); | |
194 | udelay(500); | |
195 | #endif | |
196 | ||
197 | return 512 * 1024 * 1024; | |
198 | #endif | |
199 | return CFG_SDRAM_SIZE * 1024 * 1024; | |
200 | } | |
201 | ||
202 | #endif | |
203 | ||
204 | #if defined(CONFIG_PCI) | |
205 | /* | |
206 | * Initialize PCI Devices, report devices found. | |
207 | */ | |
208 | ||
209 | #ifndef CONFIG_PCI_PNP | |
210 | static struct pci_config_table pci_fsl86xxads_config_table[] = { | |
211 | {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
212 | PCI_IDSEL_NUMBER, PCI_ANY_ID, | |
213 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, | |
214 | PCI_ENET0_MEMADDR, | |
215 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, | |
216 | {} | |
217 | }; | |
218 | #endif | |
219 | ||
220 | ||
221 | static struct pci_controller pci1_hose = { | |
222 | #ifndef CONFIG_PCI_PNP | |
223 | config_table:pci_mpc86xxcts_config_table | |
224 | #endif | |
225 | }; | |
226 | #endif /* CONFIG_PCI */ | |
227 | ||
228 | #ifdef CONFIG_PCIE1 | |
229 | static struct pci_controller pcie1_hose; | |
230 | #endif | |
231 | ||
232 | #ifdef CONFIG_PCIE2 | |
233 | static struct pci_controller pcie2_hose; | |
234 | #endif | |
235 | ||
236 | int first_free_busno = 0; | |
237 | ||
238 | void pci_init_board(void) | |
239 | { | |
240 | volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; | |
241 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
242 | uint devdisr = gur->devdisr; | |
a551cee9 JL |
243 | uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) |
244 | >> MPC8610_PORDEVSR_IO_SEL_SHIFT; | |
245 | uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) | |
246 | >> MPC8610_PORBMSR_HA_SHIFT; | |
3dd2db53 JL |
247 | |
248 | printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", | |
249 | devdisr, io_sel, host_agent); | |
250 | ||
3dd2db53 JL |
251 | #ifdef CONFIG_PCIE1 |
252 | { | |
253 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; | |
254 | extern void fsl_pci_init(struct pci_controller *hose); | |
255 | struct pci_controller *hose = &pcie1_hose; | |
256 | int pcie_configured = (io_sel == 1) || (io_sel == 4); | |
257 | int pcie_ep = (host_agent == 0) || (host_agent == 2) || | |
258 | (host_agent == 5); | |
259 | ||
260 | if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { | |
261 | printf(" PCIe 1 connected to Uli as %s (base address %x)\n", | |
262 | pcie_ep ? "End Point" : "Root Complex", | |
263 | (uint)pci); | |
264 | if (pci->pme_msg_det) | |
265 | pci->pme_msg_det = 0xffffffff; | |
266 | ||
267 | /* inbound */ | |
268 | pci_set_region(hose->regions + 0, | |
269 | CFG_PCI_MEMORY_BUS, | |
270 | CFG_PCI_MEMORY_PHYS, | |
271 | CFG_PCI_MEMORY_SIZE, | |
272 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
273 | ||
274 | /* outbound memory */ | |
275 | pci_set_region(hose->regions + 1, | |
276 | CFG_PCIE1_MEM_BASE, | |
277 | CFG_PCIE1_MEM_PHYS, | |
278 | CFG_PCIE1_MEM_SIZE, | |
279 | PCI_REGION_MEM); | |
280 | ||
281 | /* outbound io */ | |
282 | pci_set_region(hose->regions + 2, | |
283 | CFG_PCIE1_IO_BASE, | |
284 | CFG_PCIE1_IO_PHYS, | |
285 | CFG_PCIE1_IO_SIZE, | |
286 | PCI_REGION_IO); | |
287 | ||
288 | hose->region_count = 3; | |
289 | ||
290 | hose->first_busno = first_free_busno; | |
291 | pci_setup_indirect(hose, (int)&pci->cfg_addr, | |
292 | (int)&pci->cfg_data); | |
293 | ||
294 | fsl_pci_init(hose); | |
295 | ||
296 | first_free_busno = hose->last_busno + 1; | |
297 | printf(" PCI-Express 1 on bus %02x - %02x\n", | |
298 | hose->first_busno, hose->last_busno); | |
299 | ||
300 | } else | |
301 | puts(" PCI-Express 1: Disabled\n"); | |
302 | } | |
303 | #else | |
304 | puts("PCI-Express 1: Disabled\n"); | |
305 | #endif /* CONFIG_PCIE1 */ | |
306 | ||
307 | ||
308 | #ifdef CONFIG_PCIE2 | |
309 | { | |
310 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; | |
311 | extern void fsl_pci_init(struct pci_controller *hose); | |
312 | struct pci_controller *hose = &pcie2_hose; | |
313 | ||
314 | int pcie_configured = (io_sel == 0) || (io_sel == 4); | |
315 | int pcie_ep = (host_agent == 0) || (host_agent == 1) || | |
316 | (host_agent == 4); | |
317 | ||
318 | if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { | |
319 | printf(" PCI-Express 2 connected to slot as %s" \ | |
320 | " (base address %x)\n", | |
321 | pcie_ep ? "End Point" : "Root Complex", | |
322 | (uint)pci); | |
323 | if (pci->pme_msg_det) | |
324 | pci->pme_msg_det = 0xffffffff; | |
325 | ||
326 | /* inbound */ | |
327 | pci_set_region(hose->regions + 0, | |
328 | CFG_PCI_MEMORY_BUS, | |
329 | CFG_PCI_MEMORY_PHYS, | |
330 | CFG_PCI_MEMORY_SIZE, | |
331 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
332 | ||
333 | /* outbound memory */ | |
334 | pci_set_region(hose->regions + 1, | |
335 | CFG_PCIE2_MEM_BASE, | |
336 | CFG_PCIE2_MEM_PHYS, | |
337 | CFG_PCIE2_MEM_SIZE, | |
338 | PCI_REGION_MEM); | |
339 | ||
340 | /* outbound io */ | |
341 | pci_set_region(hose->regions + 2, | |
342 | CFG_PCIE2_IO_BASE, | |
343 | CFG_PCIE2_IO_PHYS, | |
344 | CFG_PCIE2_IO_SIZE, | |
345 | PCI_REGION_IO); | |
346 | ||
347 | hose->region_count = 3; | |
348 | ||
349 | hose->first_busno = first_free_busno; | |
350 | pci_setup_indirect(hose, (int)&pci->cfg_addr, | |
351 | (int)&pci->cfg_data); | |
352 | ||
353 | fsl_pci_init(hose); | |
354 | ||
355 | first_free_busno = hose->last_busno + 1; | |
356 | printf(" PCI-Express 2 on bus %02x - %02x\n", | |
357 | hose->first_busno, hose->last_busno); | |
358 | } else | |
359 | puts(" PCI-Express 2: Disabled\n"); | |
360 | } | |
361 | #else | |
362 | puts("PCI-Express 2: Disabled\n"); | |
363 | #endif /* CONFIG_PCIE2 */ | |
364 | ||
365 | ||
366 | #ifdef CONFIG_PCI1 | |
367 | { | |
368 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; | |
369 | extern void fsl_pci_init(struct pci_controller *hose); | |
370 | struct pci_controller *hose = &pci1_hose; | |
371 | int pci_agent = (host_agent >= 4) && (host_agent <= 6); | |
372 | ||
373 | if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { | |
374 | printf(" PCI connected to PCI slots as %s" \ | |
375 | " (base address %x)\n", | |
376 | pci_agent ? "Agent" : "Host", | |
377 | (uint)pci); | |
378 | ||
379 | /* inbound */ | |
380 | pci_set_region(hose->regions + 0, | |
381 | CFG_PCI_MEMORY_BUS, | |
382 | CFG_PCI_MEMORY_PHYS, | |
383 | CFG_PCI_MEMORY_SIZE, | |
384 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
385 | ||
386 | /* outbound memory */ | |
387 | pci_set_region(hose->regions + 1, | |
388 | CFG_PCI1_MEM_BASE, | |
389 | CFG_PCI1_MEM_PHYS, | |
390 | CFG_PCI1_MEM_SIZE, | |
391 | PCI_REGION_MEM); | |
392 | ||
393 | /* outbound io */ | |
394 | pci_set_region(hose->regions + 2, | |
395 | CFG_PCI1_IO_BASE, | |
396 | CFG_PCI1_IO_PHYS, | |
397 | CFG_PCI1_IO_SIZE, | |
398 | PCI_REGION_IO); | |
399 | ||
400 | hose->region_count = 3; | |
401 | ||
402 | hose->first_busno = first_free_busno; | |
403 | pci_setup_indirect(hose, (int) &pci->cfg_addr, | |
404 | (int) &pci->cfg_data); | |
405 | ||
406 | fsl_pci_init(hose); | |
407 | ||
408 | first_free_busno = hose->last_busno + 1; | |
409 | printf(" PCI on bus %02x - %02x\n", | |
410 | hose->first_busno, hose->last_busno); | |
411 | ||
412 | ||
413 | } else | |
414 | puts(" PCI: Disabled\n"); | |
415 | } | |
416 | #endif /* CONFIG_PCI1 */ | |
417 | } | |
418 | ||
1df170f8 | 419 | #if defined(CONFIG_OF_BOARD_SETUP) |
3dd2db53 JL |
420 | void |
421 | ft_board_setup(void *blob, bd_t *bd) | |
422 | { | |
1df170f8 JL |
423 | int node, tmp[2]; |
424 | const char *path; | |
3dd2db53 | 425 | |
1df170f8 JL |
426 | do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, |
427 | "timebase-frequency", bd->bi_busfreq / 4, 1); | |
428 | do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, | |
429 | "bus-frequency", bd->bi_busfreq, 1); | |
430 | do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, | |
431 | "clock-frequency", bd->bi_intfreq, 1); | |
432 | do_fixup_by_prop_u32(blob, "device_type", "soc", 4, | |
433 | "bus-frequency", bd->bi_busfreq, 1); | |
3dd2db53 | 434 | |
1df170f8 JL |
435 | do_fixup_by_compat_u32(blob, "ns16550", |
436 | "clock-frequency", bd->bi_busfreq, 1); | |
437 | ||
438 | fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); | |
439 | ||
440 | ||
441 | node = fdt_path_offset(blob, "/aliases"); | |
442 | tmp[0] = 0; | |
443 | if (node >= 0) { | |
3dd2db53 JL |
444 | |
445 | #ifdef CONFIG_PCI1 | |
1df170f8 JL |
446 | path = fdt_getprop(blob, node, "pci0", NULL); |
447 | if (path) { | |
448 | tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; | |
449 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
450 | } | |
451 | ||
3dd2db53 JL |
452 | #endif |
453 | #ifdef CONFIG_PCIE1 | |
1df170f8 JL |
454 | path = fdt_getprop(blob, node, "pci1", NULL); |
455 | if (path) { | |
456 | tmp[1] = pcie1_hose.last_busno | |
457 | - pcie1_hose.first_busno; | |
458 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
3dd2db53 JL |
459 | } |
460 | #endif | |
461 | #ifdef CONFIG_PCIE2 | |
1df170f8 JL |
462 | path = fdt_getprop(blob, node, "pci2", NULL); |
463 | if (path) { | |
464 | tmp[1] = pcie2_hose.last_busno | |
465 | - pcie2_hose.first_busno; | |
466 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
467 | } | |
3dd2db53 | 468 | #endif |
1df170f8 | 469 | } |
3dd2db53 JL |
470 | } |
471 | #endif | |
472 | ||
473 | /* | |
474 | * get_board_sys_clk | |
475 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ | |
476 | */ | |
477 | ||
478 | unsigned long | |
479 | get_board_sys_clk(ulong dummy) | |
480 | { | |
a877880c | 481 | u8 i; |
3dd2db53 JL |
482 | ulong val = 0; |
483 | ulong a; | |
484 | ||
485 | a = PIXIS_BASE + PIXIS_SPD; | |
486 | i = in8(a); | |
487 | i &= 0x07; | |
488 | ||
489 | switch (i) { | |
490 | case 0: | |
491 | val = 33333000; | |
492 | break; | |
493 | case 1: | |
494 | val = 39999600; | |
495 | break; | |
496 | case 2: | |
497 | val = 49999500; | |
498 | break; | |
499 | case 3: | |
500 | val = 66666000; | |
501 | break; | |
502 | case 4: | |
503 | val = 83332500; | |
504 | break; | |
505 | case 5: | |
506 | val = 99999000; | |
507 | break; | |
508 | case 6: | |
509 | val = 133332000; | |
510 | break; | |
511 | case 7: | |
512 | val = 166665000; | |
513 | break; | |
514 | } | |
515 | ||
516 | return val; | |
517 | } |