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debb7354 | 1 | /* |
3d98b858 | 2 | * Copyright 2006, 2007 Freescale Semiconductor. |
debb7354 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
63cec581 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
debb7354 JL |
15 | * GNU General Public License for more details. |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <pci.h> | |
25 | #include <asm/processor.h> | |
26 | #include <asm/immap_86xx.h> | |
63cec581 | 27 | #include <asm/immap_fsl_pci.h> |
6a8e5692 | 28 | #include <asm/fsl_ddr_sdram.h> |
3d98b858 | 29 | #include <asm/io.h> |
ea9f7395 JL |
30 | #include <libfdt.h> |
31 | #include <fdt_support.h> | |
0b252f50 | 32 | #include <netdev.h> |
debb7354 | 33 | |
4ce91774 | 34 | #include "../common/pixis.h" |
4d3d729c | 35 | |
4c77de3f | 36 | phys_size_t fixed_sdram(void); |
debb7354 | 37 | |
80e955c7 | 38 | int board_early_init_f(void) |
debb7354 | 39 | { |
cb5965fb | 40 | return 0; |
debb7354 JL |
41 | } |
42 | ||
80e955c7 | 43 | int checkboard(void) |
debb7354 | 44 | { |
9b55a253 WD |
45 | printf ("Board: MPC8641HPCN, System ID: 0x%02x, " |
46 | "System Version: 0x%02x, FPGA Version: 0x%02x\n", | |
7de8c21f KG |
47 | in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), |
48 | in8(PIXIS_BASE + PIXIS_PVER)); | |
debb7354 JL |
49 | return 0; |
50 | } | |
51 | ||
52 | ||
9973e3c6 | 53 | phys_size_t |
debb7354 JL |
54 | initdram(int board_type) |
55 | { | |
4c77de3f | 56 | phys_size_t dram_size = 0; |
debb7354 JL |
57 | |
58 | #if defined(CONFIG_SPD_EEPROM) | |
6a8e5692 | 59 | dram_size = fsl_ddr_sdram(); |
debb7354 | 60 | #else |
80e955c7 | 61 | dram_size = fixed_sdram(); |
debb7354 JL |
62 | #endif |
63 | ||
6d0f6bcf | 64 | #if defined(CONFIG_SYS_RAMBOOT) |
debb7354 JL |
65 | puts(" DDR: "); |
66 | return dram_size; | |
67 | #endif | |
cb5965fb | 68 | |
debb7354 JL |
69 | puts(" DDR: "); |
70 | return dram_size; | |
71 | } | |
72 | ||
73 | ||
debb7354 | 74 | #if !defined(CONFIG_SPD_EEPROM) |
5c9efb36 JL |
75 | /* |
76 | * Fixed sdram init -- doesn't use serial presence detect. | |
77 | */ | |
4c77de3f | 78 | phys_size_t |
80e955c7 | 79 | fixed_sdram(void) |
debb7354 | 80 | { |
6d0f6bcf JCPV |
81 | #if !defined(CONFIG_SYS_RAMBOOT) |
82 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; | |
80e955c7 | 83 | volatile ccsr_ddr_t *ddr = &immap->im_ddr1; |
debb7354 | 84 | |
6d0f6bcf JCPV |
85 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
86 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; | |
87 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; | |
88 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; | |
89 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; | |
90 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; | |
91 | ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; | |
92 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; | |
93 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; | |
94 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; | |
95 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; | |
96 | ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; | |
97 | ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; | |
debb7354 JL |
98 | |
99 | #if defined (CONFIG_DDR_ECC) | |
100 | ddr->err_disable = 0x0000008D; | |
101 | ddr->err_sbe = 0x00ff0000; | |
102 | #endif | |
103 | asm("sync;isync"); | |
cb5965fb | 104 | |
debb7354 JL |
105 | udelay(500); |
106 | ||
107 | #if defined (CONFIG_DDR_ECC) | |
108 | /* Enable ECC checking */ | |
6d0f6bcf | 109 | ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
debb7354 | 110 | #else |
6d0f6bcf JCPV |
111 | ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; |
112 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; | |
debb7354 JL |
113 | #endif |
114 | asm("sync; isync"); | |
cb5965fb | 115 | |
debb7354 JL |
116 | udelay(500); |
117 | #endif | |
6d0f6bcf | 118 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
debb7354 JL |
119 | } |
120 | #endif /* !defined(CONFIG_SPD_EEPROM) */ | |
121 | ||
122 | ||
123 | #if defined(CONFIG_PCI) | |
98693b85 | 124 | static struct pci_controller pci1_hose; |
80e955c7 | 125 | #endif /* CONFIG_PCI */ |
debb7354 | 126 | |
63cec581 ES |
127 | #ifdef CONFIG_PCI2 |
128 | static struct pci_controller pci2_hose; | |
129 | #endif /* CONFIG_PCI2 */ | |
130 | ||
131 | int first_free_busno = 0; | |
132 | ||
c2083e0e KG |
133 | extern int fsl_pci_setup_inbound_windows(struct pci_region *r); |
134 | extern void fsl_pci_init(struct pci_controller *hose); | |
63cec581 | 135 | |
80e955c7 | 136 | void pci_init_board(void) |
debb7354 | 137 | { |
63cec581 ES |
138 | #ifdef CONFIG_PCI1 |
139 | { | |
6d0f6bcf | 140 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; |
63cec581 | 141 | struct pci_controller *hose = &pci1_hose; |
c2083e0e | 142 | struct pci_region *r = hose->regions; |
af5d100e BB |
143 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; |
144 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
145 | uint devdisr = gur->devdisr; | |
146 | uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) | |
147 | >> MPC8641_PORDEVSR_IO_SEL_SHIFT; | |
c2083e0e | 148 | |
63cec581 | 149 | #ifdef DEBUG |
a551cee9 JL |
150 | uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) |
151 | >> MPC8641_PORBMSR_HA_SHIFT; | |
63cec581 ES |
152 | uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); |
153 | #endif | |
154 | if ((io_sel == 2 || io_sel == 3 || io_sel == 5 | |
155 | || io_sel == 6 || io_sel == 7 || io_sel == 0xF) | |
156 | && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { | |
157 | debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); | |
158 | debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); | |
159 | if (pci->pme_msg_det) { | |
160 | pci->pme_msg_det = 0xffffffff; | |
161 | debug(" with errors. Clearing. Now 0x%08x", | |
162 | pci->pme_msg_det); | |
163 | } | |
164 | debug("\n"); | |
165 | ||
166 | /* inbound */ | |
c2083e0e | 167 | r += fsl_pci_setup_inbound_windows(r); |
63cec581 ES |
168 | |
169 | /* outbound memory */ | |
c2083e0e | 170 | pci_set_region(r++, |
6d0f6bcf JCPV |
171 | CONFIG_SYS_PCI1_MEM_BASE, |
172 | CONFIG_SYS_PCI1_MEM_PHYS, | |
173 | CONFIG_SYS_PCI1_MEM_SIZE, | |
63cec581 ES |
174 | PCI_REGION_MEM); |
175 | ||
176 | /* outbound io */ | |
c2083e0e | 177 | pci_set_region(r++, |
6d0f6bcf JCPV |
178 | CONFIG_SYS_PCI1_IO_BASE, |
179 | CONFIG_SYS_PCI1_IO_PHYS, | |
180 | CONFIG_SYS_PCI1_IO_SIZE, | |
63cec581 ES |
181 | PCI_REGION_IO); |
182 | ||
c2083e0e | 183 | hose->region_count = r - hose->regions; |
63cec581 ES |
184 | |
185 | hose->first_busno=first_free_busno; | |
186 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
187 | ||
188 | fsl_pci_init(hose); | |
189 | ||
190 | first_free_busno=hose->last_busno+1; | |
191 | printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", | |
192 | hose->first_busno,hose->last_busno); | |
193 | ||
194 | /* | |
195 | * Activate ULI1575 legacy chip by performing a fake | |
196 | * memory access. Needed to make ULI RTC work. | |
197 | */ | |
6d0f6bcf JCPV |
198 | in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE |
199 | + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); | |
63cec581 ES |
200 | |
201 | } else { | |
202 | puts("PCI-EXPRESS 1: Disabled\n"); | |
203 | } | |
204 | } | |
205 | #else | |
206 | puts("PCI-EXPRESS1: Disabled\n"); | |
207 | #endif /* CONFIG_PCI1 */ | |
208 | ||
209 | #ifdef CONFIG_PCI2 | |
210 | { | |
6d0f6bcf | 211 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; |
63cec581 | 212 | struct pci_controller *hose = &pci2_hose; |
c2083e0e | 213 | struct pci_region *r = hose->regions; |
63cec581 ES |
214 | |
215 | /* inbound */ | |
c2083e0e | 216 | r += fsl_pci_setup_inbound_windows(r); |
63cec581 ES |
217 | |
218 | /* outbound memory */ | |
c2083e0e | 219 | pci_set_region(r++, |
6d0f6bcf JCPV |
220 | CONFIG_SYS_PCI2_MEM_BASE, |
221 | CONFIG_SYS_PCI2_MEM_PHYS, | |
222 | CONFIG_SYS_PCI2_MEM_SIZE, | |
63cec581 ES |
223 | PCI_REGION_MEM); |
224 | ||
225 | /* outbound io */ | |
c2083e0e | 226 | pci_set_region(r++, |
6d0f6bcf JCPV |
227 | CONFIG_SYS_PCI2_IO_BASE, |
228 | CONFIG_SYS_PCI2_IO_PHYS, | |
229 | CONFIG_SYS_PCI2_IO_SIZE, | |
63cec581 ES |
230 | PCI_REGION_IO); |
231 | ||
c2083e0e | 232 | hose->region_count = r - hose->regions; |
63cec581 ES |
233 | |
234 | hose->first_busno=first_free_busno; | |
235 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
236 | ||
237 | fsl_pci_init(hose); | |
238 | ||
239 | first_free_busno=hose->last_busno+1; | |
240 | printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", | |
241 | hose->first_busno,hose->last_busno); | |
242 | } | |
243 | #else | |
244 | puts("PCI-EXPRESS 2: Disabled\n"); | |
245 | #endif /* CONFIG_PCI2 */ | |
debb7354 | 246 | |
debb7354 JL |
247 | } |
248 | ||
13f5433f | 249 | |
ea9f7395 | 250 | #if defined(CONFIG_OF_BOARD_SETUP) |
c2083e0e | 251 | extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, |
3cbd8231 | 252 | struct pci_controller *hose); |
13f5433f | 253 | |
debb7354 JL |
254 | void |
255 | ft_board_setup(void *blob, bd_t *bd) | |
256 | { | |
13f5433f | 257 | ft_cpu_setup(blob, bd); |
ea9f7395 | 258 | |
f75e89e9 | 259 | #ifdef CONFIG_PCI1 |
c2083e0e | 260 | ft_fsl_pci_setup(blob, "pci0", &pci1_hose); |
f75e89e9 ES |
261 | #endif |
262 | #ifdef CONFIG_PCI2 | |
c2083e0e | 263 | ft_fsl_pci_setup(blob, "pci1", &pci2_hose); |
f75e89e9 | 264 | #endif |
debb7354 JL |
265 | } |
266 | #endif | |
267 | ||
debb7354 | 268 | |
239db37c HW |
269 | /* |
270 | * get_board_sys_clk | |
271 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ | |
272 | */ | |
273 | ||
80e955c7 JL |
274 | unsigned long |
275 | get_board_sys_clk(ulong dummy) | |
239db37c HW |
276 | { |
277 | u8 i, go_bit, rd_clks; | |
278 | ulong val = 0; | |
279 | ||
280 | go_bit = in8(PIXIS_BASE + PIXIS_VCTL); | |
281 | go_bit &= 0x01; | |
282 | ||
283 | rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); | |
284 | rd_clks &= 0x1C; | |
285 | ||
286 | /* | |
287 | * Only if both go bit and the SCLK bit in VCFGEN0 are set | |
288 | * should we be using the AUX register. Remember, we also set the | |
289 | * GO bit to boot from the alternate bank on the on-board flash | |
290 | */ | |
291 | ||
292 | if (go_bit) { | |
293 | if (rd_clks == 0x1c) | |
294 | i = in8(PIXIS_BASE + PIXIS_AUX); | |
295 | else | |
296 | i = in8(PIXIS_BASE + PIXIS_SPD); | |
297 | } else { | |
298 | i = in8(PIXIS_BASE + PIXIS_SPD); | |
299 | } | |
300 | ||
301 | i &= 0x07; | |
302 | ||
303 | switch (i) { | |
304 | case 0: | |
305 | val = 33000000; | |
306 | break; | |
307 | case 1: | |
308 | val = 40000000; | |
309 | break; | |
310 | case 2: | |
311 | val = 50000000; | |
312 | break; | |
313 | case 3: | |
314 | val = 66000000; | |
315 | break; | |
316 | case 4: | |
317 | val = 83000000; | |
318 | break; | |
319 | case 5: | |
320 | val = 100000000; | |
321 | break; | |
322 | case 6: | |
323 | val = 134000000; | |
324 | break; | |
325 | case 7: | |
326 | val = 166000000; | |
327 | break; | |
328 | } | |
329 | ||
330 | return val; | |
331 | } | |
0b252f50 BW |
332 | |
333 | int board_eth_init(bd_t *bis) | |
334 | { | |
335 | /* Initialize TSECs */ | |
336 | cpu_eth_init(bis); | |
337 | return pci_eth_init(bis); | |
338 | } |