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debb7354 | 1 | /* |
46f3e385 | 2 | * Copyright 2006, 2007, 2010 Freescale Semiconductor. |
debb7354 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
63cec581 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
debb7354 JL |
15 | * GNU General Public License for more details. |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <pci.h> | |
25 | #include <asm/processor.h> | |
26 | #include <asm/immap_86xx.h> | |
c8514622 | 27 | #include <asm/fsl_pci.h> |
6a8e5692 | 28 | #include <asm/fsl_ddr_sdram.h> |
3d98b858 | 29 | #include <asm/io.h> |
ea9f7395 JL |
30 | #include <libfdt.h> |
31 | #include <fdt_support.h> | |
0b252f50 | 32 | #include <netdev.h> |
debb7354 | 33 | |
4c77de3f | 34 | phys_size_t fixed_sdram(void); |
debb7354 | 35 | |
80e955c7 | 36 | int board_early_init_f(void) |
debb7354 | 37 | { |
cb5965fb | 38 | return 0; |
debb7354 JL |
39 | } |
40 | ||
80e955c7 | 41 | int checkboard(void) |
debb7354 | 42 | { |
9af9c6bd KG |
43 | u8 vboot; |
44 | u8 *pixis_base = (u8 *)PIXIS_BASE; | |
45 | ||
46 | printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " | |
47 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", | |
48 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), | |
49 | in_8(pixis_base + PIXIS_PVER)); | |
50 | ||
51 | vboot = in_8(pixis_base + PIXIS_VBOOT); | |
52 | if (vboot & PIXIS_VBOOT_FMAP) | |
53 | printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); | |
54 | else | |
55 | puts ("Promjet\n"); | |
56 | ||
2331e18b BB |
57 | #ifdef CONFIG_PHYS_64BIT |
58 | printf (" 36-bit physical address map\n"); | |
59 | #endif | |
debb7354 JL |
60 | return 0; |
61 | } | |
62 | ||
9973e3c6 | 63 | phys_size_t |
debb7354 JL |
64 | initdram(int board_type) |
65 | { | |
4c77de3f | 66 | phys_size_t dram_size = 0; |
debb7354 JL |
67 | |
68 | #if defined(CONFIG_SPD_EEPROM) | |
6a8e5692 | 69 | dram_size = fsl_ddr_sdram(); |
debb7354 | 70 | #else |
80e955c7 | 71 | dram_size = fixed_sdram(); |
debb7354 JL |
72 | #endif |
73 | ||
9ff32d8c TT |
74 | setup_ddr_bat(dram_size); |
75 | ||
debb7354 JL |
76 | puts(" DDR: "); |
77 | return dram_size; | |
78 | } | |
79 | ||
80 | ||
debb7354 | 81 | #if !defined(CONFIG_SPD_EEPROM) |
5c9efb36 JL |
82 | /* |
83 | * Fixed sdram init -- doesn't use serial presence detect. | |
84 | */ | |
4c77de3f | 85 | phys_size_t |
80e955c7 | 86 | fixed_sdram(void) |
debb7354 | 87 | { |
6d0f6bcf JCPV |
88 | #if !defined(CONFIG_SYS_RAMBOOT) |
89 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; | |
80e955c7 | 90 | volatile ccsr_ddr_t *ddr = &immap->im_ddr1; |
debb7354 | 91 | |
6d0f6bcf JCPV |
92 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
93 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; | |
94 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; | |
95 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; | |
96 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; | |
97 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; | |
e7ee23ec | 98 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
6d0f6bcf JCPV |
99 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
100 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; | |
101 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; | |
102 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; | |
103 | ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; | |
104 | ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; | |
debb7354 JL |
105 | |
106 | #if defined (CONFIG_DDR_ECC) | |
107 | ddr->err_disable = 0x0000008D; | |
108 | ddr->err_sbe = 0x00ff0000; | |
109 | #endif | |
110 | asm("sync;isync"); | |
cb5965fb | 111 | |
debb7354 JL |
112 | udelay(500); |
113 | ||
114 | #if defined (CONFIG_DDR_ECC) | |
115 | /* Enable ECC checking */ | |
e7ee23ec | 116 | ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
debb7354 | 117 | #else |
e7ee23ec | 118 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
6d0f6bcf | 119 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
debb7354 JL |
120 | #endif |
121 | asm("sync; isync"); | |
cb5965fb | 122 | |
debb7354 JL |
123 | udelay(500); |
124 | #endif | |
6d0f6bcf | 125 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
debb7354 JL |
126 | } |
127 | #endif /* !defined(CONFIG_SPD_EEPROM) */ | |
128 | ||
129 | ||
130 | #if defined(CONFIG_PCI) | |
46f3e385 | 131 | static struct pci_controller pcie1_hose; |
80e955c7 | 132 | #endif /* CONFIG_PCI */ |
debb7354 | 133 | |
46f3e385 KG |
134 | #ifdef CONFIG_PCIE2 |
135 | static struct pci_controller pcie2_hose; | |
136 | #endif /* CONFIG_PCIE2 */ | |
63cec581 ES |
137 | |
138 | int first_free_busno = 0; | |
139 | ||
80e955c7 | 140 | void pci_init_board(void) |
debb7354 | 141 | { |
9a268e4b PT |
142 | struct fsl_pci_info pci_info[2]; |
143 | int pcie_ep; | |
144 | int num = 0; | |
145 | ||
46f3e385 | 146 | #ifdef CONFIG_PCIE1 |
af5d100e BB |
147 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; |
148 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
9a268e4b | 149 | uint devdisr = in_be32(&gur->devdisr); |
af5d100e BB |
150 | uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) |
151 | >> MPC8641_PORDEVSR_IO_SEL_SHIFT; | |
3e7b6c1f | 152 | int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); |
c2083e0e | 153 | |
3e7b6c1f | 154 | if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { |
9a268e4b PT |
155 | SET_STD_PCIE_INFO(pci_info[num], 1); |
156 | pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); | |
8ca78f2c PT |
157 | printf("PCIE1: connected to ULI as %s (base addr %lx)\n", |
158 | pcie_ep ? "Endpoint" : "Root Complex", | |
159 | pci_info[num].regs); | |
9a268e4b PT |
160 | first_free_busno = fsl_pci_init_port(&pci_info[num++], |
161 | &pcie1_hose, first_free_busno); | |
63cec581 ES |
162 | |
163 | /* | |
164 | * Activate ULI1575 legacy chip by performing a fake | |
165 | * memory access. Needed to make ULI RTC work. | |
166 | */ | |
46f3e385 KG |
167 | in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT |
168 | + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); | |
63cec581 ES |
169 | |
170 | } else { | |
8ca78f2c | 171 | puts("PCIE1: disabled\n"); |
63cec581 | 172 | } |
63cec581 | 173 | #else |
8ca78f2c | 174 | puts("PCIE1: disabled\n"); |
46f3e385 | 175 | #endif /* CONFIG_PCIE1 */ |
63cec581 | 176 | |
46f3e385 | 177 | #ifdef CONFIG_PCIE2 |
9a268e4b PT |
178 | SET_STD_PCIE_INFO(pci_info[num], 2); |
179 | pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); | |
8ca78f2c PT |
180 | printf("PCIE2: connected as %s (base addr %lx)\n", |
181 | pcie_ep ? "Endpoint" : "Root Complex", | |
182 | pci_info[num].regs); | |
9a268e4b PT |
183 | first_free_busno = fsl_pci_init_port(&pci_info[num++], |
184 | &pcie2_hose, first_free_busno); | |
63cec581 | 185 | #else |
8ca78f2c | 186 | puts("PCIE2: disabled\n"); |
46f3e385 | 187 | #endif /* CONFIG_PCIE2 */ |
debb7354 | 188 | |
debb7354 JL |
189 | } |
190 | ||
13f5433f | 191 | |
ea9f7395 | 192 | #if defined(CONFIG_OF_BOARD_SETUP) |
debb7354 JL |
193 | void |
194 | ft_board_setup(void *blob, bd_t *bd) | |
195 | { | |
d52082b1 BB |
196 | int off; |
197 | u64 *tmp; | |
198 | u32 *addrcells; | |
199 | ||
13f5433f | 200 | ft_cpu_setup(blob, bd); |
ea9f7395 | 201 | |
6525d51f | 202 | FT_FSL_PCI_SETUP; |
d52082b1 BB |
203 | |
204 | /* | |
205 | * Warn if it looks like the device tree doesn't match u-boot. | |
206 | * This is just an estimation, based on the location of CCSR, | |
207 | * which is defined by the "reg" property in the soc node. | |
208 | */ | |
209 | off = fdt_path_offset(blob, "/soc8641"); | |
210 | addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); | |
211 | tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); | |
212 | ||
213 | if (tmp) { | |
214 | u64 addr; | |
3f510db5 | 215 | if (addrcells && (*addrcells == 1)) |
d52082b1 | 216 | addr = *(u32 *)tmp; |
3f510db5 BB |
217 | else |
218 | addr = *tmp; | |
d52082b1 BB |
219 | |
220 | if (addr != CONFIG_SYS_CCSRBAR_PHYS) | |
221 | printf("WARNING: The CCSRBAR address in your .dts " | |
222 | "does not match the address of the CCSR " | |
223 | "in u-boot. This means your .dts might " | |
224 | "be old.\n"); | |
225 | } | |
debb7354 JL |
226 | } |
227 | #endif | |
228 | ||
debb7354 | 229 | |
239db37c HW |
230 | /* |
231 | * get_board_sys_clk | |
232 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ | |
233 | */ | |
234 | ||
80e955c7 JL |
235 | unsigned long |
236 | get_board_sys_clk(ulong dummy) | |
239db37c HW |
237 | { |
238 | u8 i, go_bit, rd_clks; | |
239 | ulong val = 0; | |
048e7efe | 240 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
239db37c | 241 | |
048e7efe | 242 | go_bit = in_8(pixis_base + PIXIS_VCTL); |
239db37c HW |
243 | go_bit &= 0x01; |
244 | ||
048e7efe | 245 | rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); |
239db37c HW |
246 | rd_clks &= 0x1C; |
247 | ||
248 | /* | |
249 | * Only if both go bit and the SCLK bit in VCFGEN0 are set | |
250 | * should we be using the AUX register. Remember, we also set the | |
251 | * GO bit to boot from the alternate bank on the on-board flash | |
252 | */ | |
253 | ||
254 | if (go_bit) { | |
255 | if (rd_clks == 0x1c) | |
048e7efe | 256 | i = in_8(pixis_base + PIXIS_AUX); |
239db37c | 257 | else |
048e7efe | 258 | i = in_8(pixis_base + PIXIS_SPD); |
239db37c | 259 | } else { |
048e7efe | 260 | i = in_8(pixis_base + PIXIS_SPD); |
239db37c HW |
261 | } |
262 | ||
263 | i &= 0x07; | |
264 | ||
265 | switch (i) { | |
266 | case 0: | |
267 | val = 33000000; | |
268 | break; | |
269 | case 1: | |
270 | val = 40000000; | |
271 | break; | |
272 | case 2: | |
273 | val = 50000000; | |
274 | break; | |
275 | case 3: | |
276 | val = 66000000; | |
277 | break; | |
278 | case 4: | |
279 | val = 83000000; | |
280 | break; | |
281 | case 5: | |
282 | val = 100000000; | |
283 | break; | |
284 | case 6: | |
285 | val = 134000000; | |
286 | break; | |
287 | case 7: | |
288 | val = 166000000; | |
289 | break; | |
290 | } | |
291 | ||
292 | return val; | |
293 | } | |
0b252f50 BW |
294 | |
295 | int board_eth_init(bd_t *bis) | |
296 | { | |
297 | /* Initialize TSECs */ | |
298 | cpu_eth_init(bis); | |
299 | return pci_eth_init(bis); | |
300 | } | |
4ef630df PT |
301 | |
302 | void board_reset(void) | |
303 | { | |
048e7efe KG |
304 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
305 | ||
306 | out_8(pixis_base + PIXIS_RST, 0); | |
4ef630df PT |
307 | |
308 | while (1) | |
309 | ; | |
310 | } | |
f6ef8b7a | 311 | |
7649a590 | 312 | #ifdef CONFIG_MP |
f6ef8b7a BB |
313 | extern void cpu_mp_lmb_reserve(struct lmb *lmb); |
314 | ||
315 | void board_lmb_reserve(struct lmb *lmb) | |
316 | { | |
317 | cpu_mp_lmb_reserve(lmb); | |
318 | } | |
319 | #endif |