[people/ms/u-boot.git] / board / freescale / mpc8641hpcn / mpc8641hpcn.c

/*
 * Copyright 2006, 2007 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <netdev.h>

#include "../common/pixis.h"

phys_size_t fixed_sdram(void);

int board_early_init_f(void)
{
	return 0;
}

int checkboard(void)
{
	printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
		in8(PIXIS_BASE + PIXIS_PVER));
#ifdef CONFIG_PHYS_64BIT
	printf ("       36-bit physical address map\n");
#endif
	return 0;
}


phys_size_t
initdram(int board_type)
{
	phys_size_t dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();
#endif

#if defined(CONFIG_SYS_RAMBOOT)
	puts("    DDR: ");
	return dram_size;
#endif

	puts("    DDR: ");
	return dram_size;
}


#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
phys_size_t
fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
	ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;

#if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000008D;
	ddr->err_sbe = 0x00ff0000;
#endif
	asm("sync;isync");

	udelay(500);

#if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#endif
	asm("sync; isync");

	udelay(500);
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif	/* CONFIG_PCI2 */

int first_free_busno = 0;

extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);

void pci_init_board(void)
{
#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	struct pci_region *r = hose->regions;
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;

#ifdef DEBUG
	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
		>> MPC8641_PORBMSR_HA_SHIFT;
	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
#endif
	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
		debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug(" with errors.  Clearing.  Now 0x%08x",
			      pci->pme_msg_det);
		}
		debug("\n");

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_MEM_BUS,
			       CONFIG_SYS_PCI1_MEM_PHYS,
			       CONFIG_SYS_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_IO_BUS,
			       CONFIG_SYS_PCI1_IO_PHYS,
			       CONFIG_SYS_PCI1_IO_SIZE,
			       PCI_REGION_IO);

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		hose->region_count = r - hose->regions;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
				       + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));

	} else {
		puts("PCI-EXPRESS 1: Disabled\n");
	}
}
#else
	puts("PCI-EXPRESS1: Disabled\n");
#endif /* CONFIG_PCI1 */

#ifdef CONFIG_PCI2
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
	struct pci_controller *hose = &pci2_hose;
	struct pci_region *r = hose->regions;

	/* outbound memory */
	pci_set_region(r++,
		       CONFIG_SYS_PCI2_MEM_BUS,
		       CONFIG_SYS_PCI2_MEM_PHYS,
		       CONFIG_SYS_PCI2_MEM_SIZE,
		       PCI_REGION_MEM);

	/* outbound io */
	pci_set_region(r++,
		       CONFIG_SYS_PCI2_IO_BUS,
		       CONFIG_SYS_PCI2_IO_PHYS,
		       CONFIG_SYS_PCI2_IO_SIZE,
		       PCI_REGION_IO);

	/* inbound */
	r += fsl_pci_setup_inbound_windows(r);

	hose->region_count = r - hose->regions;

	hose->first_busno=first_free_busno;
	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

	fsl_pci_init(hose);

	first_free_busno=hose->last_busno+1;
	printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
		hose->first_busno,hose->last_busno);
}
#else
	puts("PCI-EXPRESS 2: Disabled\n");
#endif /* CONFIG_PCI2 */

}


#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
			struct pci_controller *hose);

void
ft_board_setup(void *blob, bd_t *bd)
{
	int off;
	u64 *tmp;
	u32 *addrcells;

	ft_cpu_setup(blob, bd);

#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif

	/*
	 * Warn if it looks like the device tree doesn't match u-boot.
	 * This is just an estimation, based on the location of CCSR,
	 * which is defined by the "reg" property in the soc node.
	 */
	off = fdt_path_offset(blob, "/soc8641");
	addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
	tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);

	if (tmp) {
		u64 addr;
		if (addrcells && (*addrcells == 1))
			addr = *(u32 *)tmp;
		else
			addr = *tmp;

		if (addr != CONFIG_SYS_CCSRBAR_PHYS)
			printf("WARNING: The CCSRBAR address in your .dts "
			       "does not match the address of the CCSR "
			       "in u-boot.  This means your .dts might "
			       "be old.\n");
	}
}
#endif


/*
 * get_board_sys_clk
 *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 */

unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;

	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in8(PIXIS_BASE + PIXIS_AUX);
		else
			i = in8(PIXIS_BASE + PIXIS_SPD);
	} else {
		i = in8(PIXIS_BASE + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33000000;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66000000;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 134000000;
		break;
	case 7:
		val = 166000000;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
	/* Initialize TSECs */
	cpu_eth_init(bis);
	return pci_eth_init(bis);
}

void board_reset(void)
{
	out8(PIXIS_BASE + PIXIS_RST, 0);

	while (1)
		;
}

#if (CONFIG_NUM_CPUS > 1)
extern void cpu_mp_lmb_reserve(struct lmb *lmb);

void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
debb7354	1	/*
3d98b858	2	* Copyright 2006, 2007 Freescale Semiconductor.
debb7354 JL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
63cec581	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
debb7354 JL	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <pci.h>
	25	#include <asm/processor.h>
	26	#include <asm/immap_86xx.h>
63cec581	27	#include <asm/immap_fsl_pci.h>
6a8e5692	28	#include <asm/fsl_ddr_sdram.h>
3d98b858	29	#include <asm/io.h>
ea9f7395 JL	30	#include <libfdt.h>
ea9f7395 JL	31	#include <fdt_support.h>
0b252f50	32	#include <netdev.h>
debb7354	33
4ce91774	34	#include "../common/pixis.h"
4d3d729c	35
4c77de3f	36	phys_size_t fixed_sdram(void);
debb7354	37
80e955c7	38	int board_early_init_f(void)
debb7354	39	{
cb5965fb	40	return 0;
debb7354 JL	41	}
debb7354 JL	42
80e955c7	43	int checkboard(void)
debb7354	44	{
9b55a253 WD	45	printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
9b55a253 WD	46	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
7de8c21f KG	47	in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
7de8c21f KG	48	in8(PIXIS_BASE + PIXIS_PVER));
2331e18b BB	49	#ifdef CONFIG_PHYS_64BIT
	50	printf (" 36-bit physical address map\n");
	51	#endif
debb7354 JL	52	return 0;
	53	}
	54
	55
9973e3c6	56	phys_size_t
debb7354 JL	57	initdram(int board_type)
debb7354 JL	58	{
4c77de3f	59	phys_size_t dram_size = 0;
debb7354 JL	60
debb7354 JL	61	#if defined(CONFIG_SPD_EEPROM)
6a8e5692	62	dram_size = fsl_ddr_sdram();
debb7354	63	#else
80e955c7	64	dram_size = fixed_sdram();
debb7354 JL	65	#endif
debb7354 JL	66
6d0f6bcf	67	#if defined(CONFIG_SYS_RAMBOOT)
debb7354 JL	68	puts(" DDR: ");
	69	return dram_size;
	70	#endif
cb5965fb	71
debb7354 JL	72	puts(" DDR: ");
	73	return dram_size;
	74	}
	75
	76
debb7354	77	#if !defined(CONFIG_SPD_EEPROM)
5c9efb36 JL	78	/*
	79	* Fixed sdram init -- doesn't use serial presence detect.
	80	*/
4c77de3f	81	phys_size_t
80e955c7	82	fixed_sdram(void)
debb7354	83	{
6d0f6bcf JCPV	84	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	85	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
80e955c7	86	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
debb7354	87
6d0f6bcf JCPV	88	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	89	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	90	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	91	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	92	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	93	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	94	ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
	95	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	96	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	97	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	98	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	99	ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
	100	ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
debb7354 JL	101
	102	#if defined (CONFIG_DDR_ECC)
	103	ddr->err_disable = 0x0000008D;
	104	ddr->err_sbe = 0x00ff0000;
	105	#endif
	106	asm("sync;isync");
cb5965fb	107
debb7354 JL	108	udelay(500);
	109
	110	#if defined (CONFIG_DDR_ECC)
	111	/* Enable ECC checking */
6d0f6bcf	112	ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL \| 0x20000000);
debb7354	113	#else
6d0f6bcf JCPV	114	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
6d0f6bcf JCPV	115	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
debb7354 JL	116	#endif
debb7354 JL	117	asm("sync; isync");
cb5965fb	118
debb7354 JL	119	udelay(500);
debb7354 JL	120	#endif
6d0f6bcf	121	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
debb7354 JL	122	}
	123	#endif /* !defined(CONFIG_SPD_EEPROM) */
	124
	125
	126	#if defined(CONFIG_PCI)
98693b85	127	static struct pci_controller pci1_hose;
80e955c7	128	#endif /* CONFIG_PCI */
debb7354	129
63cec581 ES	130	#ifdef CONFIG_PCI2
	131	static struct pci_controller pci2_hose;
	132	#endif /* CONFIG_PCI2 */
	133
	134	int first_free_busno = 0;
	135
c2083e0e KG	136	extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
c2083e0e KG	137	extern void fsl_pci_init(struct pci_controller *hose);
63cec581	138
80e955c7	139	void pci_init_board(void)
debb7354	140	{
63cec581 ES	141	#ifdef CONFIG_PCI1
63cec581 ES	142	{
6d0f6bcf	143	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
63cec581	144	struct pci_controller *hose = &pci1_hose;
c2083e0e	145	struct pci_region *r = hose->regions;
af5d100e BB	146	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
	147	volatile ccsr_gur_t *gur = &immap->im_gur;
	148	uint devdisr = gur->devdisr;
	149	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
	150	>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
c2083e0e	151
63cec581	152	#ifdef DEBUG
a551cee9 JL	153	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
a551cee9 JL	154	>> MPC8641_PORBMSR_HA_SHIFT;
63cec581 ES	155	uint pex1_agent = (host1_agent == 0) \|\| (host1_agent == 1);
	156	#endif
	157	if ((io_sel == 2 \|\| io_sel == 3 \|\| io_sel == 5
	158	\|\| io_sel == 6 \|\| io_sel == 7 \|\| io_sel == 0xF)
	159	&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
	160	debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
	161	debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
	162	if (pci->pme_msg_det) {
	163	pci->pme_msg_det = 0xffffffff;
	164	debug(" with errors. Clearing. Now 0x%08x",
	165	pci->pme_msg_det);
	166	}
	167	debug("\n");
	168
63cec581	169	/* outbound memory */
c2083e0e	170	pci_set_region(r++,
49f46f3b	171	CONFIG_SYS_PCI1_MEM_BUS,
6d0f6bcf JCPV	172	CONFIG_SYS_PCI1_MEM_PHYS,
6d0f6bcf JCPV	173	CONFIG_SYS_PCI1_MEM_SIZE,
63cec581 ES	174	PCI_REGION_MEM);
	175
	176	/* outbound io */
c2083e0e	177	pci_set_region(r++,
49f46f3b	178	CONFIG_SYS_PCI1_IO_BUS,
6d0f6bcf JCPV	179	CONFIG_SYS_PCI1_IO_PHYS,
6d0f6bcf JCPV	180	CONFIG_SYS_PCI1_IO_SIZE,
63cec581 ES	181	PCI_REGION_IO);
63cec581 ES	182
2ecca340 BB	183	/* inbound */
	184	r += fsl_pci_setup_inbound_windows(r);
	185
c2083e0e	186	hose->region_count = r - hose->regions;
63cec581 ES	187
	188	hose->first_busno=first_free_busno;
	189	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	190
	191	fsl_pci_init(hose);
	192
	193	first_free_busno=hose->last_busno+1;
	194	printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
	195	hose->first_busno,hose->last_busno);
	196
	197	/*
	198	* Activate ULI1575 legacy chip by performing a fake
	199	* memory access. Needed to make ULI RTC work.
	200	*/
49f46f3b	201	in_be32((unsigned ) ((char )(CONFIG_SYS_PCI1_MEM_VIRT
6d0f6bcf	202	+ CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
63cec581 ES	203
	204	} else {
	205	puts("PCI-EXPRESS 1: Disabled\n");
	206	}
	207	}
	208	#else
	209	puts("PCI-EXPRESS1: Disabled\n");
	210	#endif /* CONFIG_PCI1 */
	211
	212	#ifdef CONFIG_PCI2
	213	{
6d0f6bcf	214	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI2_ADDR;
63cec581	215	struct pci_controller *hose = &pci2_hose;
c2083e0e	216	struct pci_region *r = hose->regions;
63cec581	217
63cec581	218	/* outbound memory */
c2083e0e	219	pci_set_region(r++,
49f46f3b	220	CONFIG_SYS_PCI2_MEM_BUS,
6d0f6bcf JCPV	221	CONFIG_SYS_PCI2_MEM_PHYS,
6d0f6bcf JCPV	222	CONFIG_SYS_PCI2_MEM_SIZE,
63cec581 ES	223	PCI_REGION_MEM);
	224
	225	/* outbound io */
c2083e0e	226	pci_set_region(r++,
49f46f3b	227	CONFIG_SYS_PCI2_IO_BUS,
6d0f6bcf JCPV	228	CONFIG_SYS_PCI2_IO_PHYS,
6d0f6bcf JCPV	229	CONFIG_SYS_PCI2_IO_SIZE,
63cec581 ES	230	PCI_REGION_IO);
63cec581 ES	231
2ecca340 BB	232	/* inbound */
	233	r += fsl_pci_setup_inbound_windows(r);
	234
c2083e0e	235	hose->region_count = r - hose->regions;
63cec581 ES	236
	237	hose->first_busno=first_free_busno;
	238	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	239
	240	fsl_pci_init(hose);
	241
	242	first_free_busno=hose->last_busno+1;
	243	printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
	244	hose->first_busno,hose->last_busno);
	245	}
	246	#else
	247	puts("PCI-EXPRESS 2: Disabled\n");
	248	#endif /* CONFIG_PCI2 */
debb7354	249
debb7354 JL	250	}
debb7354 JL	251
13f5433f	252
ea9f7395	253	#if defined(CONFIG_OF_BOARD_SETUP)
c2083e0e	254	extern void ft_fsl_pci_setup(void blob, const char pci_alias,
3cbd8231	255	struct pci_controller *hose);
13f5433f	256
debb7354 JL	257	void
	258	ft_board_setup(void blob, bd_t bd)
	259	{
d52082b1 BB	260	int off;
	261	u64 *tmp;
	262	u32 *addrcells;
	263
13f5433f	264	ft_cpu_setup(blob, bd);
ea9f7395	265
f75e89e9	266	#ifdef CONFIG_PCI1
c2083e0e	267	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
f75e89e9 ES	268	#endif
f75e89e9 ES	269	#ifdef CONFIG_PCI2
c2083e0e	270	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
f75e89e9	271	#endif
d52082b1 BB	272
	273	/*
	274	* Warn if it looks like the device tree doesn't match u-boot.
	275	* This is just an estimation, based on the location of CCSR,
	276	* which is defined by the "reg" property in the soc node.
	277	*/
	278	off = fdt_path_offset(blob, "/soc8641");
	279	addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
	280	tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
	281
	282	if (tmp) {
	283	u64 addr;
3f510db5	284	if (addrcells && (*addrcells == 1))
d52082b1	285	addr = (u32 )tmp;
3f510db5 BB	286	else
3f510db5 BB	287	addr = *tmp;
d52082b1 BB	288
	289	if (addr != CONFIG_SYS_CCSRBAR_PHYS)
	290	printf("WARNING: The CCSRBAR address in your .dts "
	291	"does not match the address of the CCSR "
	292	"in u-boot. This means your .dts might "
	293	"be old.\n");
	294	}
debb7354 JL	295	}
	296	#endif
	297
debb7354	298
239db37c HW	299	/*
	300	* get_board_sys_clk
	301	* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
	302	*/
	303
80e955c7 JL	304	unsigned long
80e955c7 JL	305	get_board_sys_clk(ulong dummy)
239db37c HW	306	{
	307	u8 i, go_bit, rd_clks;
	308	ulong val = 0;
	309
	310	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	311	go_bit &= 0x01;
	312
	313	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	314	rd_clks &= 0x1C;
	315
	316	/*
	317	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	318	* should we be using the AUX register. Remember, we also set the
	319	* GO bit to boot from the alternate bank on the on-board flash
	320	*/
	321
	322	if (go_bit) {
	323	if (rd_clks == 0x1c)
	324	i = in8(PIXIS_BASE + PIXIS_AUX);
	325	else
	326	i = in8(PIXIS_BASE + PIXIS_SPD);
	327	} else {
	328	i = in8(PIXIS_BASE + PIXIS_SPD);
	329	}
	330
	331	i &= 0x07;
	332
	333	switch (i) {
	334	case 0:
	335	val = 33000000;
	336	break;
	337	case 1:
	338	val = 40000000;
	339	break;
	340	case 2:
	341	val = 50000000;
	342	break;
	343	case 3:
	344	val = 66000000;
	345	break;
	346	case 4:
	347	val = 83000000;
	348	break;
	349	case 5:
	350	val = 100000000;
	351	break;
	352	case 6:
	353	val = 134000000;
	354	break;
	355	case 7:
	356	val = 166000000;
	357	break;
	358	}
	359
	360	return val;
	361	}
0b252f50 BW	362
	363	int board_eth_init(bd_t *bis)
	364	{
	365	/* Initialize TSECs */
	366	cpu_eth_init(bis);
	367	return pci_eth_init(bis);
	368	}
4ef630df PT	369
	370	void board_reset(void)
	371	{
	372	out8(PIXIS_BASE + PIXIS_RST, 0);
	373
	374	while (1)
	375	;
	376	}
f6ef8b7a BB	377
	378	#if (CONFIG_NUM_CPUS > 1)
	379	extern void cpu_mp_lmb_reserve(struct lmb *lmb);
	380
	381	void board_lmb_reserve(struct lmb *lmb)
	382	{
	383	cpu_mp_lmb_reserve(lmb);
	384	}
	385	#endif