]> git.ipfire.org Git - thirdparty/u-boot.git/blame - board/freescale/mx31ads/u-boot.lds
Coding Style cleanup: remove trailing white space
[thirdparty/u-boot.git] / board / freescale / mx31ads / u-boot.lds
CommitLineData
b5dc9b30
GL
1/*
2 * January 2004 - Changed to support H4 device
3 * Copyright (c) 2004 Texas Instruments
4 *
5 * (C) Copyright 2002
792a09eb 6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
b5dc9b30 7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
b5dc9b30
GL
9 */
10
11OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
12OUTPUT_ARCH(arm)
13ENTRY(_start)
14SECTIONS
15{
16 . = 0x00000000;
17
18 . = ALIGN(4);
19 .text :
20 {
d026dec8 21 *(.__image_copy_start)
d23ff682
GL
22 /* WARNING - the following is hand-optimized to fit within */
23 /* the sector layout of our flash chips! XXX FIXME XXX */
24
1a9a91dc
BT
25 arch/arm/cpu/arm1136/start.o (.text*)
26 board/freescale/mx31ads/libmx31ads.o (.text*)
27 arch/arm/lib/libarm.o (.text*)
28 net/libnet.o (.text*)
29 drivers/mtd/libmtd.o (.text*)
d23ff682
GL
30
31 . = DEFINED(env_offset) ? env_offset : .;
1a9a91dc 32 common/env_embedded.o(.text*)
d23ff682 33
1a9a91dc 34 *(.text*)
b5dc9b30 35 }
b5dc9b30 36 . = ALIGN(4);
1a9a91dc 37 .rodata : { *(.rodata*) }
b5dc9b30
GL
38
39 . = ALIGN(4);
4ac2e2d6 40 .data : {
1a9a91dc 41 *(.data*)
4ac2e2d6 42 }
b5dc9b30
GL
43
44 . = ALIGN(4);
b5dc9b30 45
55675142
MV
46 . = ALIGN(4);
47 .u_boot_list : {
ef123c52 48 KEEP(*(SORT(.u_boot_list*)));
55675142 49 }
b5dc9b30
GL
50
51 . = ALIGN(4);
4ac2e2d6 52
d026dec8
AA
53 .image_copy_end :
54 {
55 *(.__image_copy_end)
56 }
b736e4b9 57
47bd65ef
AA
58 .rel_dyn_start :
59 {
60 *(.__rel_dyn_start)
61 }
62
4ac2e2d6 63 .rel.dyn : {
4ac2e2d6 64 *(.rel*)
47bd65ef
AA
65 }
66
67 .rel_dyn_end :
68 {
69 *(.__rel_dyn_end)
4ac2e2d6
FE
70 }
71
4ac2e2d6
FE
72 _end = .;
73
f84a7b8f
AA
74/*
75 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
76 * __bss_base and __bss_limit are for linker only (overlay ordering)
77 */
78
3ebd1cbc
AA
79 .bss_start __rel_dyn_start (OVERLAY) : {
80 KEEP(*(.__bss_start));
f84a7b8f 81 __bss_base = .;
3ebd1cbc
AA
82 }
83
f84a7b8f 84 .bss __bss_base (OVERLAY) : {
3ebd1cbc 85 *(.bss*)
4ac2e2d6 86 . = ALIGN(4);
f84a7b8f 87 __bss_limit = .;
3ebd1cbc 88 }
f84a7b8f
AA
89 .bss_end __bss_limit (OVERLAY) : {
90 KEEP(*(.__bss_end));
4ac2e2d6
FE
91 }
92
93 /DISCARD/ : { *(.bss*) }
09d81184 94 /DISCARD/ : { *(.dynsym) }
4ac2e2d6
FE
95 /DISCARD/ : { *(.dynstr*) }
96 /DISCARD/ : { *(.dynsym*) }
97 /DISCARD/ : { *(.dynamic*) }
98 /DISCARD/ : { *(.hash*) }
99 /DISCARD/ : { *(.plt*) }
100 /DISCARD/ : { *(.interp*) }
101 /DISCARD/ : { *(.gnu*) }
b5dc9b30 102}