[people/ms/u-boot.git] / board / freescale / mx31pdk / mx31pdk.c

/*
 *
 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
 *
 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <watchdog.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
	mxc_hw_watchdog_reset();
}
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
				PHYS_SDRAM_1_SIZE);
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}

int board_early_init_f(void)
{
	/* CS5: CPLD incl. network controller */
	__REG(CSCR_U(5)) = 0x0000d843;
	__REG(CSCR_L(5)) = 0x22252521;
	__REG(CSCR_A(5)) = 0x22220a00;

	/* Setup UART1 and SPI2 pins */
	mx31_uart1_hw_init();
	mx31_spi2_hw_init();

	return 0;
}

int board_init(void)
{
	gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int board_late_init(void)
{
#ifdef CONFIG_HW_WATCHDOG
	mxc_hw_watchdog_enable();
#endif
	return 0;
}

int checkboard(void)
{
	printf("Board: MX31PDK\n");
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC911X
	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
	return rc;
}
Commit	Line	Data
8449f287 ML	1	/*
	2	*
	3	* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
	4	*
	5	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26
	27	#include <common.h>
736fead8	28	#include <netdev.h>
86271115 SB	29	#include <asm/arch/clock.h>
86271115 SB	30	#include <asm/arch/imx-regs.h>
b73850f7	31	#include <watchdog.h>
8449f287 ML	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
b73850f7 FE	35	#ifdef CONFIG_HW_WATCHDOG
	36	void hw_watchdog_reset(void)
	37	{
	38	mxc_hw_watchdog_reset();
	39	}
	40	#endif
	41
8449f287	42	int dram_init(void)
ed3df72d FE	43	{
	44	/* dram_init must store complete ramsize in gd->ram_size */
	45	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
	46	PHYS_SDRAM_1_SIZE);
	47	return 0;
	48	}
	49
	50	void dram_init_banksize(void)
8449f287 ML	51	{
	52	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	53	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
8449f287 ML	54	}
8449f287 ML	55
9b6442f9	56	int board_early_init_f(void)
8449f287 ML	57	{
	58	/* CS5: CPLD incl. network controller */
	59	__REG(CSCR_U(5)) = 0x0000d843;
	60	__REG(CSCR_L(5)) = 0x22252521;
	61	__REG(CSCR_A(5)) = 0x22220a00;
	62
	63	/* Setup UART1 and SPI2 pins */
	64	mx31_uart1_hw_init();
	65	mx31_spi2_hw_init();
	66
9b6442f9 FE	67	return 0;
	68	}
	69
	70	int board_init(void)
	71	{
8449f287 ML	72	gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
	73	/* adress of boot parameters */
	74	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	75
	76	return 0;
	77	}
	78
b73850f7 FE	79	int board_late_init(void)
	80	{
	81	#ifdef CONFIG_HW_WATCHDOG
	82	mxc_hw_watchdog_enable();
	83	#endif
	84	return 0;
	85	}
	86
8449f287 ML	87	int checkboard(void)
8449f287 ML	88	{
e9e0790c	89	printf("Board: MX31PDK\n");
8449f287 ML	90	return 0;
8449f287 ML	91	}
736fead8 BW	92
	93	int board_eth_init(bd_t *bis)
	94	{
	95	int rc = 0;
	96	#ifdef CONFIG_SMC911X
	97	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	98	#endif
	99	return rc;
	100	}