[people/ms/u-boot.git] / board / freescale / mx31pdk / mx31pdk.c

/*
 *
 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
 *
 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
#include <pmic.h>
#include <fsl_pmic.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
	mxc_hw_watchdog_reset();
}
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				PHYS_SDRAM_1_SIZE);
	return 0;
}

int board_early_init_f(void)
{
	/* CS5: CPLD incl. network controller */
	static const struct mxc_weimcs cs5 = {
		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
		CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
		CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
	};

	mxc_setup_weimcs(5, &cs5);

	/* Setup UART1 and SPI2 pins */
	mx31_uart1_hw_init();
	mx31_spi2_hw_init();

	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int board_late_init(void)
{
	u32 val;
	struct pmic *p;

	pmic_init();
	p = get_pmic();

	/* Enable RTC battery */
	pmic_reg_read(p, REG_POWER_CTL0, &val);
	pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
	mxc_hw_watchdog_enable();
#endif
	return 0;
}

int checkboard(void)
{
	printf("Board: MX31PDK\n");
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC911X
	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
	return rc;
}
Commit	Line	Data
8449f287 ML	1	/*
	2	*
	3	* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
	4	*
	5	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26
	27	#include <common.h>
736fead8	28	#include <netdev.h>
86271115 SB	29	#include <asm/arch/clock.h>
86271115 SB	30	#include <asm/arch/imx-regs.h>
47c5455a	31	#include <asm/arch/sys_proto.h>
b73850f7	32	#include <watchdog.h>
1f83d009 FE	33	#include <pmic.h>
1f83d009 FE	34	#include <fsl_pmic.h>
8449f287 ML	35
	36	DECLARE_GLOBAL_DATA_PTR;
	37
b73850f7 FE	38	#ifdef CONFIG_HW_WATCHDOG
	39	void hw_watchdog_reset(void)
	40	{
	41	mxc_hw_watchdog_reset();
	42	}
	43	#endif
	44
8449f287	45	int dram_init(void)
ed3df72d FE	46	{
ed3df72d FE	47	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	48	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
ed3df72d FE	49	PHYS_SDRAM_1_SIZE);
	50	return 0;
	51	}
	52
9b6442f9	53	int board_early_init_f(void)
8449f287 ML	54	{
8449f287 ML	55	/* CS5: CPLD incl. network controller */
47c5455a HR	56	static const struct mxc_weimcs cs5 = {
	57	/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
	58	CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
	59	/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
	60	CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
	61	/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
	62	CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
	63	};
	64
	65	mxc_setup_weimcs(5, &cs5);
8449f287 ML	66
	67	/* Setup UART1 and SPI2 pins */
	68	mx31_uart1_hw_init();
	69	mx31_spi2_hw_init();
	70
9b6442f9 FE	71	return 0;
	72	}
	73
	74	int board_init(void)
	75	{
8449f287 ML	76	/* adress of boot parameters */
	77	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	78
	79	return 0;
	80	}
	81
b73850f7 FE	82	int board_late_init(void)
b73850f7 FE	83	{
1f83d009 FE	84	u32 val;
	85	struct pmic *p;
	86
	87	pmic_init();
	88	p = get_pmic();
	89
	90	/* Enable RTC battery */
	91	pmic_reg_read(p, REG_POWER_CTL0, &val);
	92	pmic_reg_write(p, REG_POWER_CTL0, val \| COINCHEN);
	93	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
b73850f7 FE	94	#ifdef CONFIG_HW_WATCHDOG
	95	mxc_hw_watchdog_enable();
	96	#endif
	97	return 0;
	98	}
	99
8449f287 ML	100	int checkboard(void)
8449f287 ML	101	{
e9e0790c	102	printf("Board: MX31PDK\n");
8449f287 ML	103	return 0;
8449f287 ML	104	}
736fead8 BW	105
	106	int board_eth_init(bd_t *bis)
	107	{
	108	int rc = 0;
	109	#ifdef CONFIG_SMC911X
	110	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	111	#endif
	112	return rc;
	113	}