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eae4988b SB |
1 | /* |
2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
eae4988b SB |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/errno.h> | |
12 | #include <asm/arch/imx-regs.h> | |
13 | #include <asm/arch/crm_regs.h> | |
a2ac1b3a | 14 | #include <asm/arch/clock.h> |
105c9eaf | 15 | #include <asm/arch/iomux-mx35.h> |
eae4988b | 16 | #include <i2c.h> |
c7336815 | 17 | #include <power/pmic.h> |
eae4988b | 18 | #include <fsl_pmic.h> |
3292539e SB |
19 | #include <mmc.h> |
20 | #include <fsl_esdhc.h> | |
eae4988b SB |
21 | #include <mc9sdz60.h> |
22 | #include <mc13892.h> | |
23 | #include <linux/types.h> | |
a4adedd4 | 24 | #include <asm/gpio.h> |
eae4988b SB |
25 | #include <asm/arch/sys_proto.h> |
26 | #include <netdev.h> | |
27 | ||
9660e442 HR |
28 | #ifndef CONFIG_BOARD_LATE_INIT |
29 | #error "CONFIG_BOARD_LATE_INIT must be set for this board" | |
eae4988b SB |
30 | #endif |
31 | ||
32 | #ifndef CONFIG_BOARD_EARLY_INIT_F | |
33 | #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" | |
34 | #endif | |
35 | ||
eae4988b SB |
36 | DECLARE_GLOBAL_DATA_PTR; |
37 | ||
38 | int dram_init(void) | |
39 | { | |
6b5acfc1 SB |
40 | u32 size1, size2; |
41 | ||
42 | size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); | |
43 | size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); | |
44 | ||
45 | gd->ram_size = size1 + size2; | |
eae4988b SB |
46 | |
47 | return 0; | |
48 | } | |
49 | ||
6b5acfc1 SB |
50 | void dram_init_banksize(void) |
51 | { | |
52 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
53 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
54 | ||
55 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
56 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
57 | } | |
58 | ||
105c9eaf BT |
59 | #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) |
60 | ||
eae4988b SB |
61 | static void setup_iomux_i2c(void) |
62 | { | |
105c9eaf BT |
63 | static const iomux_v3_cfg_t i2c1_pads[] = { |
64 | NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), | |
65 | NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), | |
66 | }; | |
eae4988b SB |
67 | |
68 | /* setup pins for I2C1 */ | |
105c9eaf | 69 | imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); |
eae4988b SB |
70 | } |
71 | ||
72 | ||
73 | static void setup_iomux_spi(void) | |
74 | { | |
105c9eaf BT |
75 | static const iomux_v3_cfg_t spi_pads[] = { |
76 | MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, | |
77 | MX35_PAD_CSPI1_MISO__CSPI1_MISO, | |
78 | MX35_PAD_CSPI1_SS0__CSPI1_SS0, | |
79 | MX35_PAD_CSPI1_SS1__CSPI1_SS1, | |
80 | MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, | |
81 | }; | |
82 | ||
83 | imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); | |
eae4988b SB |
84 | } |
85 | ||
105c9eaf BT |
86 | #define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \ |
87 | PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) | |
88 | #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) | |
89 | ||
961a7628 BT |
90 | static void setup_iomux_usbotg(void) |
91 | { | |
105c9eaf BT |
92 | static const iomux_v3_cfg_t usbotg_pads[] = { |
93 | NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, | |
94 | USBOTG_OUT_PAD_CTRL), | |
95 | NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, | |
96 | USBOTG_IN_PAD_CTRL), | |
97 | }; | |
961a7628 BT |
98 | |
99 | /* Set up pins for USBOTG. */ | |
105c9eaf | 100 | imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads)); |
961a7628 BT |
101 | } |
102 | ||
105c9eaf BT |
103 | #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) |
104 | ||
eae4988b SB |
105 | static void setup_iomux_fec(void) |
106 | { | |
105c9eaf BT |
107 | static const iomux_v3_cfg_t fec_pads[] = { |
108 | NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL | | |
109 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
110 | NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL | | |
111 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
112 | NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL | | |
113 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
114 | NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL | | |
115 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
116 | NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL | | |
117 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
118 | NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL), | |
119 | NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL), | |
120 | NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL), | |
121 | NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL | | |
122 | PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), | |
123 | NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL), | |
124 | NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL | | |
125 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
126 | NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL | | |
127 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
128 | NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL | | |
129 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
130 | NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL), | |
131 | NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL | | |
132 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
133 | NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL), | |
134 | NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL | | |
135 | PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), | |
136 | NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL), | |
137 | }; | |
eae4988b SB |
138 | |
139 | /* setup pins for FEC */ | |
105c9eaf | 140 | imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
eae4988b SB |
141 | } |
142 | ||
143 | int board_early_init_f(void) | |
144 | { | |
145 | struct ccm_regs *ccm = | |
146 | (struct ccm_regs *)IMX_CCM_BASE; | |
147 | ||
148 | /* enable clocks */ | |
149 | writel(readl(&ccm->cgr0) | | |
150 | MXC_CCM_CGR0_EMI_MASK | | |
34a31bf5 | 151 | MXC_CCM_CGR0_EDIO_MASK | |
eae4988b SB |
152 | MXC_CCM_CGR0_EPIT1_MASK, |
153 | &ccm->cgr0); | |
154 | ||
155 | writel(readl(&ccm->cgr1) | | |
156 | MXC_CCM_CGR1_FEC_MASK | | |
157 | MXC_CCM_CGR1_GPIO1_MASK | | |
158 | MXC_CCM_CGR1_GPIO2_MASK | | |
159 | MXC_CCM_CGR1_GPIO3_MASK | | |
160 | MXC_CCM_CGR1_I2C1_MASK | | |
161 | MXC_CCM_CGR1_I2C2_MASK | | |
162 | MXC_CCM_CGR1_IPU_MASK, | |
163 | &ccm->cgr1); | |
164 | ||
165 | /* Setup NAND */ | |
166 | __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); | |
167 | ||
168 | setup_iomux_i2c(); | |
961a7628 | 169 | setup_iomux_usbotg(); |
eae4988b SB |
170 | setup_iomux_fec(); |
171 | setup_iomux_spi(); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | int board_init(void) | |
177 | { | |
178 | gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ | |
179 | /* address of boot parameters */ | |
180 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static inline int pmic_detect(void) | |
186 | { | |
5213d6e4 | 187 | unsigned int id; |
c7336815 ŁM |
188 | struct pmic *p = pmic_get("FSL_PMIC"); |
189 | if (!p) | |
190 | return -ENODEV; | |
eae4988b | 191 | |
5213d6e4 | 192 | pmic_reg_read(p, REG_IDENTIFICATION, &id); |
eae4988b SB |
193 | |
194 | id = (id >> 6) & 0x7; | |
195 | if (id == 0x7) | |
196 | return 1; | |
197 | return 0; | |
198 | } | |
199 | ||
200 | u32 get_board_rev(void) | |
201 | { | |
202 | int rev; | |
203 | ||
204 | rev = pmic_detect(); | |
205 | ||
206 | return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; | |
207 | } | |
208 | ||
209 | int board_late_init(void) | |
210 | { | |
211 | u8 val; | |
212 | u32 pmic_val; | |
5213d6e4 | 213 | struct pmic *p; |
c7336815 ŁM |
214 | int ret; |
215 | ||
570aa2fa | 216 | ret = pmic_init(I2C_0); |
c7336815 ŁM |
217 | if (ret) |
218 | return ret; | |
eae4988b SB |
219 | |
220 | if (pmic_detect()) { | |
c7336815 | 221 | p = pmic_get("FSL_PMIC"); |
105c9eaf | 222 | imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B); |
eae4988b | 223 | |
5213d6e4 SB |
224 | pmic_reg_read(p, REG_SETTING_0, &pmic_val); |
225 | pmic_reg_write(p, REG_SETTING_0, | |
226 | pmic_val | VO_1_30V | VO_1_50V); | |
227 | pmic_reg_read(p, REG_MODE_0, &pmic_val); | |
228 | pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); | |
eae4988b | 229 | |
105c9eaf | 230 | imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5); |
eae4988b | 231 | |
68088cee | 232 | gpio_direction_output(IMX_GPIO_NR(1, 5), 1); |
eae4988b SB |
233 | } |
234 | ||
235 | val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; | |
236 | mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); | |
237 | mdelay(200); | |
238 | ||
239 | val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; | |
240 | mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); | |
241 | mdelay(200); | |
242 | ||
243 | val |= 0x80; | |
244 | mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); | |
245 | ||
eae4988b | 246 | /* Print board revision */ |
ba901df4 | 247 | printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); |
eae4988b SB |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
252 | int board_eth_init(bd_t *bis) | |
253 | { | |
eae4988b | 254 | #if defined(CONFIG_SMC911X) |
a05f4ab6 FE |
255 | int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
256 | if (rc) | |
257 | return rc; | |
eae4988b | 258 | #endif |
a05f4ab6 | 259 | return cpu_eth_init(bis); |
eae4988b | 260 | } |
3292539e SB |
261 | |
262 | #if defined(CONFIG_FSL_ESDHC) | |
263 | ||
264 | struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; | |
265 | ||
266 | int board_mmc_init(bd_t *bis) | |
267 | { | |
105c9eaf BT |
268 | static const iomux_v3_cfg_t sdhc1_pads[] = { |
269 | MX35_PAD_SD1_CMD__ESDHC1_CMD, | |
270 | MX35_PAD_SD1_CLK__ESDHC1_CLK, | |
271 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0, | |
272 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | |
273 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | |
274 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | |
275 | }; | |
276 | ||
3292539e | 277 | /* configure pins for SDHC1 only */ |
105c9eaf | 278 | imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); |
3292539e | 279 | |
a2ac1b3a | 280 | esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); |
3292539e SB |
281 | return fsl_esdhc_initialize(bis, &esdhc_cfg); |
282 | } | |
283 | ||
284 | int board_mmc_getcd(struct mmc *mmc) | |
285 | { | |
286 | return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); | |
287 | } | |
288 | #endif |