[people/ms/u-boot.git] / board / freescale / mx53loco / mx53loco.c

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 * Jason Liu <r64343@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	u32 size1, size2;

	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);

	gd->ram_size = size1 + size2;

	return 0;
}
void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}

static void setup_iomux_uart(void)
{
	/* UART1 RXD */
	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);

	/* UART1 TXD */
	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
}

#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
	/* request VBUS power enable pin, GPIO[8}, gpio7 */
	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
	return 0;
}
#endif

static void setup_iomux_fec(void)
{
	/*FEC_MDIO*/
	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);

	/*FEC_MDC*/
	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);

	/* FEC RXD1 */
	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC RXD0 */
	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	 /* FEC TXD1 */
	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);

	/* FEC TXD0 */
	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);

	/* FEC TX_EN */
	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);

	/* FEC TX_CLK */
	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC RX_ER */
	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC CRS */
	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR, 1},
	{MMC_SDHC3_BASE_ADDR, 1},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
	gpio_direction_input(75);
	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
	gpio_direction_input(77);

	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
		ret = !gpio_get_value(77); /* GPIO3_13 */
	else
		ret = !gpio_get_value(75); /* GPIO3_11 */

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	u32 index;
	s32 status = 0;

	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
		switch (index) {
		case 0:
			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA0,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA1,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA2,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA3,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_EIM_DA13,
						IOMUX_CONFIG_ALT1);

			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
				PAD_CTL_DRV_HIGH);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			break;
		case 1:
			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
						IOMUX_CONFIG_ALT2);
			mxc_request_iomux(MX53_PIN_ATA_IORDY,
						IOMUX_CONFIG_ALT2);
			mxc_request_iomux(MX53_PIN_ATA_DATA8,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA9,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA10,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA11,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA0,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA1,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA2,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA3,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_EIM_DA11,
						IOMUX_CONFIG_ALT1);

			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
				PAD_CTL_DRV_HIGH);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);

			break;
		default:
			printf("Warning: you configured more ESDHC controller"
				"(%d) as supported by the board(2)\n",
				CONFIG_SYS_FSL_ESDHC_NUM);
			return status;
		}
		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
	}

	return status;
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	mxc_set_sata_internal_clock();

	return 0;
}

int checkboard(void)
{
	puts("Board: MX53 LOCO\n");

	return 0;
}
Commit	Line	Data
938080dc JL	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	* Jason Liu <r64343@freescale.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/io.h>
	26	#include <asm/arch/imx-regs.h>
	27	#include <asm/arch/mx5x_pins.h>
	28	#include <asm/arch/sys_proto.h>
	29	#include <asm/arch/crm_regs.h>
f92e4e6c	30	#include <asm/arch/clock.h>
938080dc JL	31	#include <asm/arch/iomux.h>
	32	#include <asm/arch/clock.h>
	33	#include <asm/errno.h>
	34	#include <netdev.h>
	35	#include <i2c.h>
	36	#include <mmc.h>
	37	#include <fsl_esdhc.h>
50410078	38	#include <asm/gpio.h>
938080dc JL	39
	40	DECLARE_GLOBAL_DATA_PTR;
	41
938080dc JL	42	int dram_init(void)
	43	{
	44	u32 size1, size2;
	45
a55d23cc AA	46	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
a55d23cc AA	47	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
938080dc JL	48
	49	gd->ram_size = size1 + size2;
	50
	51	return 0;
	52	}
	53	void dram_init_banksize(void)
	54	{
	55	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	56	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	57
	58	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	59	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
	60	}
	61
	62	static void setup_iomux_uart(void)
	63	{
	64	/* UART1 RXD */
	65	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
	66	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
	67	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	68	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	69	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU \|
	70	PAD_CTL_ODE_OPENDRAIN_ENABLE);
	71	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
	72
	73	/* UART1 TXD */
	74	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
	75	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
	76	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	77	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	78	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU \|
	79	PAD_CTL_ODE_OPENDRAIN_ENABLE);
	80	}
	81
45cf6ada	82	#ifdef CONFIG_USB_EHCI_MX5
60bae5ef	83	int board_ehci_hcd_init(int port)
45cf6ada WG	84	{
	85	/* request VBUS power enable pin, GPIO[8}, gpio7 */
	86	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
	87	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
	88	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
60bae5ef	89	return 0;
45cf6ada WG	90	}
	91	#endif
	92
938080dc JL	93	static void setup_iomux_fec(void)
	94	{
	95	/FEC_MDIO/
	96	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
	97	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
	98	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	99	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	100	PAD_CTL_22K_PU \| PAD_CTL_ODE_OPENDRAIN_ENABLE);
	101	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
	102
	103	/FEC_MDC/
	104	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
	105	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
	106
	107	/* FEC RXD1 */
	108	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
	109	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
	110	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	111
	112	/* FEC RXD0 */
	113	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
	114	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
	115	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	116
	117	/* FEC TXD1 */
	118	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
	119	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
	120
	121	/* FEC TXD0 */
	122	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
	123	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
	124
	125	/* FEC TX_EN */
	126	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
	127	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
	128
	129	/* FEC TX_CLK */
	130	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
	131	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
	132	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	133
	134	/* FEC RX_ER */
	135	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
	136	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
	137	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	138
	139	/* FEC CRS */
	140	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
	141	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
	142	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	143	}
	144
	145	#ifdef CONFIG_FSL_ESDHC
	146	struct fsl_esdhc_cfg esdhc_cfg[2] = {
	147	{MMC_SDHC1_BASE_ADDR, 1},
	148	{MMC_SDHC3_BASE_ADDR, 1},
	149	};
	150
314284b1	151	int board_mmc_getcd(struct mmc *mmc)
938080dc JL	152	{
938080dc JL	153	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
314284b1	154	int ret;
938080dc	155
73128aad	156	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
a091be76	157	gpio_direction_input(75);
73128aad	158	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
a091be76	159	gpio_direction_input(77);
73128aad	160
938080dc	161	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
314284b1	162	ret = !gpio_get_value(77); /* GPIO3_13 */
938080dc	163	else
314284b1	164	ret = !gpio_get_value(75); /* GPIO3_11 */
938080dc	165
314284b1	166	return ret;
938080dc JL	167	}
	168
	169	int board_mmc_init(bd_t *bis)
	170	{
	171	u32 index;
	172	s32 status = 0;
	173
	174	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
	175	switch (index) {
	176	case 0:
	177	mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
	178	mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
	179	mxc_request_iomux(MX53_PIN_SD1_DATA0,
	180	IOMUX_CONFIG_ALT0);
	181	mxc_request_iomux(MX53_PIN_SD1_DATA1,
	182	IOMUX_CONFIG_ALT0);
	183	mxc_request_iomux(MX53_PIN_SD1_DATA2,
	184	IOMUX_CONFIG_ALT0);
	185	mxc_request_iomux(MX53_PIN_SD1_DATA3,
	186	IOMUX_CONFIG_ALT0);
	187	mxc_request_iomux(MX53_PIN_EIM_DA13,
	188	IOMUX_CONFIG_ALT1);
	189
	190	mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
	191	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	192	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	193	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU);
	194	mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
	195	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	196	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU \|
	197	PAD_CTL_DRV_HIGH);
	198	mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
	199	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	200	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	201	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	202	mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
	203	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	204	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	205	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	206	mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
	207	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	208	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	209	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	210	mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
	211	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	212	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	213	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	214	break;
	215	case 1:
	216	mxc_request_iomux(MX53_PIN_ATA_RESET_B,
	217	IOMUX_CONFIG_ALT2);
	218	mxc_request_iomux(MX53_PIN_ATA_IORDY,
	219	IOMUX_CONFIG_ALT2);
	220	mxc_request_iomux(MX53_PIN_ATA_DATA8,
	221	IOMUX_CONFIG_ALT4);
	222	mxc_request_iomux(MX53_PIN_ATA_DATA9,
	223	IOMUX_CONFIG_ALT4);
	224	mxc_request_iomux(MX53_PIN_ATA_DATA10,
	225	IOMUX_CONFIG_ALT4);
	226	mxc_request_iomux(MX53_PIN_ATA_DATA11,
	227	IOMUX_CONFIG_ALT4);
	228	mxc_request_iomux(MX53_PIN_ATA_DATA0,
	229	IOMUX_CONFIG_ALT4);
	230	mxc_request_iomux(MX53_PIN_ATA_DATA1,
231	IOMUX_CONFIG_ALT4);
232	mxc_request_iomux(MX53_PIN_ATA_DATA2,
233	IOMUX_CONFIG_ALT4);
234	mxc_request_iomux(MX53_PIN_ATA_DATA3,
235	IOMUX_CONFIG_ALT4);
236	mxc_request_iomux(MX53_PIN_EIM_DA11,
237	IOMUX_CONFIG_ALT1);
238
239	mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
240	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
241	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
242	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU);
243	mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
244	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
245	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU \|
246	PAD_CTL_DRV_HIGH);
247	mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
248	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
249	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
250	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
251	mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
252	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
253	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
254	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
255	mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
256	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
257	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
258	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
259	mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
260	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
261	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
262	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
263	mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
264	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
265	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
266	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
267	mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
268	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
269	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
270	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
271	mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
272	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
273	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
274	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
275	mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
276	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
277	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
278	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
279
280	break;
281	default:
282	printf("Warning: you configured more ESDHC controller"
283	"(%d) as supported by the board(2)\n",
284	CONFIG_SYS_FSL_ESDHC_NUM);
285	return status;
286	}
287	status \|= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
288	}
289
290	return status;
291	}
292	#endif
293
294	int board_early_init_f(void)
295	{
296	setup_iomux_uart();
297	setup_iomux_fec();
298
299	return 0;
300	}
301
302	int board_init(void)
303	{
938080dc JL	304	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
938080dc JL	305
f92e4e6c SB	306	mxc_set_sata_internal_clock();
f92e4e6c SB	307
938080dc JL	308	return 0;
	309	}
	310
	311	int checkboard(void)
	312	{
	313	puts("Board: MX53 LOCO\n");
	314
	315	return 0;
	316	}