[people/ms/u-boot.git] / board / freescale / mx53loco / mx53loco.c

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 * Jason Liu <r64343@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/gpio.h>
#include <pmic.h>
#include <dialog_pmic.h>
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>

#define MX53LOCO_LCD_POWER		(2 * 32 + 24)	/* GPIO3_24 */

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	u32 size1, size2;

	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);

	gd->ram_size = size1 + size2;

	return 0;
}
void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}

u32 get_board_rev(void)
{
	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
	struct fuse_bank *bank = &iim->bank[0];
	struct fuse_bank0_regs *fuse =
		(struct fuse_bank0_regs *)bank->fuse_regs;

	int rev = readl(&fuse->gp[6]);

	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}

static void setup_iomux_uart(void)
{
	/* UART1 RXD */
	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);

	/* UART1 TXD */
	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
}

#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
	/* request VBUS power enable pin, GPIO7_8 */
	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
	return 0;
}
#endif

static void setup_iomux_fec(void)
{
	/*FEC_MDIO*/
	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);

	/*FEC_MDC*/
	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);

	/* FEC RXD1 */
	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC RXD0 */
	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	 /* FEC TXD1 */
	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);

	/* FEC TXD0 */
	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);

	/* FEC TX_EN */
	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);

	/* FEC TX_CLK */
	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC RX_ER */
	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC CRS */
	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR, 1},
	{MMC_SDHC3_BASE_ADDR, 1},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret;

	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
	gpio_direction_input(75);
	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
	gpio_direction_input(77);

	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
		ret = !gpio_get_value(77); /* GPIO3_13 */
	else
		ret = !gpio_get_value(75); /* GPIO3_11 */

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	u32 index;
	s32 status = 0;

	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
		switch (index) {
		case 0:
			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA0,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA1,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA2,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_SD1_DATA3,
						IOMUX_CONFIG_ALT0);
			mxc_request_iomux(MX53_PIN_EIM_DA13,
						IOMUX_CONFIG_ALT1);

			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
				PAD_CTL_DRV_HIGH);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			break;
		case 1:
			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
						IOMUX_CONFIG_ALT2);
			mxc_request_iomux(MX53_PIN_ATA_IORDY,
						IOMUX_CONFIG_ALT2);
			mxc_request_iomux(MX53_PIN_ATA_DATA8,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA9,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA10,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA11,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA0,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA1,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA2,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_ATA_DATA3,
						IOMUX_CONFIG_ALT4);
			mxc_request_iomux(MX53_PIN_EIM_DA11,
						IOMUX_CONFIG_ALT1);

			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
				PAD_CTL_DRV_HIGH);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);

			break;
		default:
			printf("Warning: you configured more ESDHC controller"
				"(%d) as supported by the board(2)\n",
				CONFIG_SYS_FSL_ESDHC_NUM);
			return status;
		}
		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
	}

	return status;
}
#endif

static void setup_iomux_i2c(void)
{
	/* I2C1 SDA */
	mxc_request_iomux(MX53_PIN_CSI0_D8,
		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
		INPUT_CTL_PATH0);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
		PAD_CTL_PUE_PULL |
		PAD_CTL_ODE_OPENDRAIN_ENABLE);
	/* I2C1 SCL */
	mxc_request_iomux(MX53_PIN_CSI0_D9,
		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
		INPUT_CTL_PATH0);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
		PAD_CTL_PUE_PULL |
		PAD_CTL_ODE_OPENDRAIN_ENABLE);
}

static int power_init(void)
{
	unsigned int val;
	int ret = -1;
	struct pmic *p;

	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
		pmic_dialog_init();
		p = get_pmic();

		/* Set VDDA to 1.25V */
		val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
		ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);

		ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
		val |= DA9052_SUPPLY_VBCOREGO;
		ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);

		/* Set Vcc peripheral to 1.30V */
		ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
		ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
	}

	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
		pmic_init();
		p = get_pmic();

		/* Set VDDGP to 1.25V for 1GHz on SW1 */
		pmic_reg_read(p, REG_SW_0, &val);
		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
		ret = pmic_reg_write(p, REG_SW_0, val);

		/* Set VCC as 1.30V on SW2 */
		pmic_reg_read(p, REG_SW_1, &val);
		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
		ret |= pmic_reg_write(p, REG_SW_1, val);

		/* Set global reset timer to 4s */
		pmic_reg_read(p, REG_POWER_CTL2, &val);
		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
		ret |= pmic_reg_write(p, REG_POWER_CTL2, val);

		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
		pmic_reg_read(p, REG_MODE_0, &val);
		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
		ret |= pmic_reg_write(p, REG_MODE_0, val);

		/* Set SWBST to 5V in auto mode */
		val = SWBST_AUTO;
		ret |= pmic_reg_write(p, SWBST_CTRL, val);
	}

	return ret;
}

static void clock_1GHz(void)
{
	int ret;
	u32 ref_clk = CONFIG_SYS_MX5_HCLK;
	/*
	 * After increasing voltage to 1.25V, we can switch
	 * CPU clock to 1GHz and DDR to 400MHz safely
	 */
	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
	if (ret)
		printf("CPU:   Switch CPU clock to 1GHZ failed\n");

	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
	if (ret)
		printf("CPU:   Switch DDR clock to 400MHz failed\n");
}

static struct fb_videomode claa_wvga = {
	.name		= "CLAA07LC0ACW",
	.refresh	= 57,
	.xres		= 800,
	.yres		= 480,
	.pixclock	= 37037,
	.left_margin	= 40,
	.right_margin	= 60,
	.upper_margin	= 10,
	.lower_margin	= 10,
	.hsync_len	= 20,
	.vsync_len	= 10,
	.sync		= 0,
	.vmode		= FB_VMODE_NONINTERLACED
};

void lcd_iomux(void)
{
	mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);

	/* Turn on GPIO backlight */
	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
	gpio_direction_output(MX53LOCO_LCD_POWER, 1);

	/* Turn on display contrast */
	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
}

void lcd_enable(void)
{
	int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
	if (ret)
		printf("LCD cannot be configured: %d\n", ret);
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();
	lcd_iomux();

	return 0;
}

int print_cpuinfo(void)
{
	u32 cpurev;

	cpurev = get_cpu_rev();
	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
		(cpurev & 0xFF000) >> 12,
		(cpurev & 0x000F0) >> 4,
		(cpurev & 0x0000F) >> 0,
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
	printf("Reset cause: %s\n", get_reset_cause());
	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	setup_iomux_i2c();
	if (!power_init())
		clock_1GHz();
	print_cpuinfo();

	setenv("stdout", "serial");

	return 0;
}
#endif

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	mxc_set_sata_internal_clock();

	lcd_enable();

	return 0;
}

int checkboard(void)
{
	puts("Board: MX53 LOCO\n");

	return 0;
}
Commit	Line	Data
938080dc JL	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	3	* Jason Liu <r64343@freescale.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/io.h>
	26	#include <asm/arch/imx-regs.h>
	27	#include <asm/arch/mx5x_pins.h>
	28	#include <asm/arch/sys_proto.h>
	29	#include <asm/arch/crm_regs.h>
f92e4e6c	30	#include <asm/arch/clock.h>
938080dc JL	31	#include <asm/arch/iomux.h>
	32	#include <asm/arch/clock.h>
	33	#include <asm/errno.h>
	34	#include <netdev.h>
	35	#include <i2c.h>
	36	#include <mmc.h>
	37	#include <fsl_esdhc.h>
50410078	38	#include <asm/gpio.h>
e7e33722 FE	39	#include <pmic.h>
e7e33722 FE	40	#include <dialog_pmic.h>
5b547f3c	41	#include <fsl_pmic.h>
f714b0a9 FE	42	#include <linux/fb.h>
	43	#include <ipu_pixfmt.h>
	44
	45	#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */
938080dc JL	46
	47	DECLARE_GLOBAL_DATA_PTR;
	48
938080dc JL	49	int dram_init(void)
	50	{
	51	u32 size1, size2;
	52
a55d23cc AA	53	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
a55d23cc AA	54	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
938080dc JL	55
	56	gd->ram_size = size1 + size2;
	57
	58	return 0;
	59	}
	60	void dram_init_banksize(void)
	61	{
	62	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	63	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	64
	65	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	66	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
	67	}
	68
54cd1dee FE	69	u32 get_board_rev(void)
	70	{
	71	struct iim_regs iim = (struct iim_regs )IMX_IIM_BASE;
	72	struct fuse_bank *bank = &iim->bank[0];
	73	struct fuse_bank0_regs *fuse =
	74	(struct fuse_bank0_regs *)bank->fuse_regs;
	75
	76	int rev = readl(&fuse->gp[6]);
	77
	78	return (get_cpu_rev() & ~(0xF << 8)) \| (rev & 0xF) << 8;
	79	}
	80
938080dc JL	81	static void setup_iomux_uart(void)
	82	{
	83	/* UART1 RXD */
	84	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
	85	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
	86	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	87	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	88	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU \|
	89	PAD_CTL_ODE_OPENDRAIN_ENABLE);
	90	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
	91
	92	/* UART1 TXD */
	93	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
	94	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
	95	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	96	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	97	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU \|
	98	PAD_CTL_ODE_OPENDRAIN_ENABLE);
	99	}
	100
45cf6ada	101	#ifdef CONFIG_USB_EHCI_MX5
60bae5ef	102	int board_ehci_hcd_init(int port)
45cf6ada	103	{
6ecaee82	104	/* request VBUS power enable pin, GPIO7_8 */
45cf6ada	105	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
6ecaee82	106	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
60bae5ef	107	return 0;
45cf6ada WG	108	}
	109	#endif
	110
938080dc JL	111	static void setup_iomux_fec(void)
	112	{
	113	/FEC_MDIO/
	114	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
	115	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
	116	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	117	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	118	PAD_CTL_22K_PU \| PAD_CTL_ODE_OPENDRAIN_ENABLE);
	119	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
	120
	121	/FEC_MDC/
	122	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
	123	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
	124
	125	/* FEC RXD1 */
	126	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
	127	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
	128	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	129
	130	/* FEC RXD0 */
	131	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
	132	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
	133	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	134
	135	/* FEC TXD1 */
	136	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
	137	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
	138
	139	/* FEC TXD0 */
	140	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
	141	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
	142
	143	/* FEC TX_EN */
	144	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
	145	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
	146
	147	/* FEC TX_CLK */
	148	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
	149	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
	150	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	151
	152	/* FEC RX_ER */
	153	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
	154	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
	155	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	156
	157	/* FEC CRS */
	158	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
	159	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
	160	PAD_CTL_HYS_ENABLE \| PAD_CTL_PKE_ENABLE);
	161	}
	162
	163	#ifdef CONFIG_FSL_ESDHC
	164	struct fsl_esdhc_cfg esdhc_cfg[2] = {
	165	{MMC_SDHC1_BASE_ADDR, 1},
	166	{MMC_SDHC3_BASE_ADDR, 1},
	167	};
	168
314284b1	169	int board_mmc_getcd(struct mmc *mmc)
938080dc JL	170	{
938080dc JL	171	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
314284b1	172	int ret;
938080dc	173
73128aad	174	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
a091be76	175	gpio_direction_input(75);
73128aad	176	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
a091be76	177	gpio_direction_input(77);
73128aad	178
938080dc	179	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
314284b1	180	ret = !gpio_get_value(77); /* GPIO3_13 */
938080dc	181	else
314284b1	182	ret = !gpio_get_value(75); /* GPIO3_11 */
938080dc	183
314284b1	184	return ret;
938080dc JL	185	}
	186
	187	int board_mmc_init(bd_t *bis)
	188	{
	189	u32 index;
	190	s32 status = 0;
	191
	192	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
	193	switch (index) {
	194	case 0:
	195	mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
	196	mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
	197	mxc_request_iomux(MX53_PIN_SD1_DATA0,
	198	IOMUX_CONFIG_ALT0);
	199	mxc_request_iomux(MX53_PIN_SD1_DATA1,
	200	IOMUX_CONFIG_ALT0);
	201	mxc_request_iomux(MX53_PIN_SD1_DATA2,
	202	IOMUX_CONFIG_ALT0);
	203	mxc_request_iomux(MX53_PIN_SD1_DATA3,
	204	IOMUX_CONFIG_ALT0);
	205	mxc_request_iomux(MX53_PIN_EIM_DA13,
	206	IOMUX_CONFIG_ALT1);
	207
	208	mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
	209	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	210	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	211	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU);
	212	mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
	213	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	214	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU \|
	215	PAD_CTL_DRV_HIGH);
	216	mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
	217	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	218	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	219	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	220	mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
	221	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	222	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	223	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	224	mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
	225	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	226	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	227	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	228	mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
	229	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
	230	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
	231	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
	232	break;
	233	case 1:
	234	mxc_request_iomux(MX53_PIN_ATA_RESET_B,
	235	IOMUX_CONFIG_ALT2);
	236	mxc_request_iomux(MX53_PIN_ATA_IORDY,
	237	IOMUX_CONFIG_ALT2);
	238	mxc_request_iomux(MX53_PIN_ATA_DATA8,
	239	IOMUX_CONFIG_ALT4);
	240	mxc_request_iomux(MX53_PIN_ATA_DATA9,
	241	IOMUX_CONFIG_ALT4);
	242	mxc_request_iomux(MX53_PIN_ATA_DATA10,
	243	IOMUX_CONFIG_ALT4);
	244	mxc_request_iomux(MX53_PIN_ATA_DATA11,
	245	IOMUX_CONFIG_ALT4);
	246	mxc_request_iomux(MX53_PIN_ATA_DATA0,
	247	IOMUX_CONFIG_ALT4);
	248	mxc_request_iomux(MX53_PIN_ATA_DATA1,
249	IOMUX_CONFIG_ALT4);
250	mxc_request_iomux(MX53_PIN_ATA_DATA2,
251	IOMUX_CONFIG_ALT4);
252	mxc_request_iomux(MX53_PIN_ATA_DATA3,
253	IOMUX_CONFIG_ALT4);
254	mxc_request_iomux(MX53_PIN_EIM_DA11,
255	IOMUX_CONFIG_ALT1);
256
257	mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
258	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
259	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
260	PAD_CTL_HYS_ENABLE \| PAD_CTL_100K_PU);
261	mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
262	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
263	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU \|
264	PAD_CTL_DRV_HIGH);
265	mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
266	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
267	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
268	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
269	mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
270	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
271	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
272	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
273	mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
274	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
275	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
276	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
277	mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
278	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
279	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
280	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
281	mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
282	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
283	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
284	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
285	mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
286	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
287	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
288	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
289	mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
290	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
291	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
292	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
293	mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
294	PAD_CTL_HYS_ENABLE \| PAD_CTL_DRV_HIGH \|
295	PAD_CTL_PUE_PULL \| PAD_CTL_PKE_ENABLE \|
296	PAD_CTL_HYS_ENABLE \| PAD_CTL_47K_PU);
297
298	break;
299	default:
300	printf("Warning: you configured more ESDHC controller"
301	"(%d) as supported by the board(2)\n",
302	CONFIG_SYS_FSL_ESDHC_NUM);
303	return status;
304	}
305	status \|= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
306	}
307
308	return status;
309	}
310	#endif
311
e7e33722 FE	312	static void setup_iomux_i2c(void)
	313	{
	314	/* I2C1 SDA */
	315	mxc_request_iomux(MX53_PIN_CSI0_D8,
	316	IOMUX_CONFIG_ALT5 \| IOMUX_CONFIG_SION);
	317	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
	318	INPUT_CTL_PATH0);
	319	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
	320	PAD_CTL_SRE_FAST \| PAD_CTL_DRV_HIGH \|
	321	PAD_CTL_100K_PU \| PAD_CTL_PKE_ENABLE \|
	322	PAD_CTL_PUE_PULL \|
	323	PAD_CTL_ODE_OPENDRAIN_ENABLE);
	324	/* I2C1 SCL */
	325	mxc_request_iomux(MX53_PIN_CSI0_D9,
	326	IOMUX_CONFIG_ALT5 \| IOMUX_CONFIG_SION);
	327	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
	328	INPUT_CTL_PATH0);
	329	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
	330	PAD_CTL_SRE_FAST \| PAD_CTL_DRV_HIGH \|
	331	PAD_CTL_100K_PU \| PAD_CTL_PKE_ENABLE \|
	332	PAD_CTL_PUE_PULL \|
	333	PAD_CTL_ODE_OPENDRAIN_ENABLE);
	334	}
	335
	336	static int power_init(void)
	337	{
5b547f3c FE	338	unsigned int val;
5b547f3c FE	339	int ret = -1;
e7e33722 FE	340	struct pmic *p;
e7e33722 FE	341
5b547f3c FE	342	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
	343	pmic_dialog_init();
	344	p = get_pmic();
e7e33722	345
5b547f3c FE	346	/* Set VDDA to 1.25V */
	347	val = DA9052_BUCKCORE_BCOREEN \| DA_BUCKCORE_VBCORE_1_250V;
	348	ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
e7e33722	349
5b547f3c FE	350	ret \|= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
	351	val \|= DA9052_SUPPLY_VBCOREGO;
	352	ret \|= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
e7e33722	353
5b547f3c FE	354	/* Set Vcc peripheral to 1.30V */
	355	ret \|= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
	356	ret \|= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
	357	}
	358
	359	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
	360	pmic_init();
	361	p = get_pmic();
	362
	363	/* Set VDDGP to 1.25V for 1GHz on SW1 */
	364	pmic_reg_read(p, REG_SW_0, &val);
	365	val = (val & ~SWx_VOLT_MASK_MC34708) \| SWx_1_250V_MC34708;
	366	ret = pmic_reg_write(p, REG_SW_0, val);
	367
	368	/* Set VCC as 1.30V on SW2 */
	369	pmic_reg_read(p, REG_SW_1, &val);
	370	val = (val & ~SWx_VOLT_MASK_MC34708) \| SWx_1_300V_MC34708;
	371	ret \|= pmic_reg_write(p, REG_SW_1, val);
	372
	373	/* Set global reset timer to 4s */
	374	pmic_reg_read(p, REG_POWER_CTL2, &val);
	375	val = (val & ~TIMER_MASK_MC34708) \| TIMER_4S_MC34708;
	376	ret \|= pmic_reg_write(p, REG_POWER_CTL2, val);
768a0597 FE	377
	378	/* Set VUSBSEL and VUSBEN for USB PHY supply*/
	379	pmic_reg_read(p, REG_MODE_0, &val);
	380	val \|= (VUSBSEL_MC34708 \| VUSBEN_MC34708);
	381	ret \|= pmic_reg_write(p, REG_MODE_0, val);
	382
	383	/* Set SWBST to 5V in auto mode */
	384	val = SWBST_AUTO;
	385	ret \|= pmic_reg_write(p, SWBST_CTRL, val);
5b547f3c	386	}
e7e33722 FE	387
	388	return ret;
	389	}
	390
	391	static void clock_1GHz(void)
	392	{
	393	int ret;
	394	u32 ref_clk = CONFIG_SYS_MX5_HCLK;
	395	/*
	396	* After increasing voltage to 1.25V, we can switch
	397	* CPU clock to 1GHz and DDR to 400MHz safely
	398	*/
	399	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
	400	if (ret)
	401	printf("CPU: Switch CPU clock to 1GHZ failed\n");
	402
	403	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
	404	ret \|= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
	405	if (ret)
	406	printf("CPU: Switch DDR clock to 400MHz failed\n");
	407	}
	408
f714b0a9 FE	409	static struct fb_videomode claa_wvga = {
	410	.name = "CLAA07LC0ACW",
	411	.refresh = 57,
	412	.xres = 800,
	413	.yres = 480,
	414	.pixclock = 37037,
	415	.left_margin = 40,
	416	.right_margin = 60,
	417	.upper_margin = 10,
	418	.lower_margin = 10,
	419	.hsync_len = 20,
	420	.vsync_len = 10,
	421	.sync = 0,
	422	.vmode = FB_VMODE_NONINTERLACED
	423	};
	424
	425	void lcd_iomux(void)
	426	{
	427	mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
	428	mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
	429	mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
	430	mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
	431	mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
	432	mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
	433	mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
	434	mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
	435	mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
	436	mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
	437	mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
	438	mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
	439	mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
	440	mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
	441	mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
	442	mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
	443	mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
	444	mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
	445	mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
	446	mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
	447	mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
	448	mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
	449	mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
	450	mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
	451	mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
	452	mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
	453	mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
	454	mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
	455
	456	/* Turn on GPIO backlight */
	457	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
	458	gpio_direction_output(MX53LOCO_LCD_POWER, 1);
	459
	460	/* Turn on display contrast */
	461	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
	462	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
	463	}
	464
	465	void lcd_enable(void)
	466	{
	467	int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
	468	if (ret)
	469	printf("LCD cannot be configured: %d\n", ret);
	470	}
	471
938080dc JL	472	int board_early_init_f(void)
	473	{
	474	setup_iomux_uart();
	475	setup_iomux_fec();
f714b0a9	476	lcd_iomux();
938080dc JL	477
	478	return 0;
	479	}
	480
1fc56f1c FE	481	int print_cpuinfo(void)
	482	{
	483	u32 cpurev;
	484
	485	cpurev = get_cpu_rev();
	486	printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
	487	(cpurev & 0xFF000) >> 12,
	488	(cpurev & 0x000F0) >> 4,
	489	(cpurev & 0x0000F) >> 0,
	490	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	491	printf("Reset cause: %s\n", get_reset_cause());
	492	return 0;
	493	}
	494
	495	#ifdef CONFIG_BOARD_LATE_INIT
	496	int board_late_init(void)
	497	{
e7e33722 FE	498	setup_iomux_i2c();
	499	if (!power_init())
	500	clock_1GHz();
1fc56f1c	501	print_cpuinfo();
e7e33722	502
f714b0a9 FE	503	setenv("stdout", "serial");
f714b0a9 FE	504
1fc56f1c FE	505	return 0;
	506	}
	507	#endif
	508
938080dc JL	509	int board_init(void)
938080dc JL	510	{
938080dc JL	511	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
938080dc JL	512
f92e4e6c SB	513	mxc_set_sata_internal_clock();
f92e4e6c SB	514
f714b0a9 FE	515	lcd_enable();
f714b0a9 FE	516
938080dc JL	517	return 0;
	518	}
	519
	520	int checkboard(void)
	521	{
	522	puts("Board: MX53 LOCO\n");
	523
	524	return 0;
	525	}