[people/ms/u-boot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/spi.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/imx-common/video.h>
#include <asm/arch/crm_regs.h>
#include <pca953x.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
			PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)

#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

static iomux_v3_cfg_t const uart4_pads[] = {
	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
};

/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
		.gp = IMX_GPIO_NR(2, 30)
	},
	.sda = {
		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
		.gp = IMX_GPIO_NR(4, 13)
	}
};

/*
 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 * Compass Sensor, Accelerometer, Res Touch
 */
static struct i2c_pads_info i2c_pad_info2 = {
	.scl = {
		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
		.gp = IMX_GPIO_NR(1, 3)
	},
	.sda = {
		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
		.gp = IMX_GPIO_NR(3, 18)
	}
};

static iomux_v3_cfg_t const i2c3_pads[] = {
	MX6_PAD_EIM_A24__GPIO5_IO04		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const port_exp[] = {
	MX6_PAD_SD2_DAT0__GPIO1_IO15		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

/*Define for building port exp gpio, pin starts from 0*/
#define PORTEXP_IO_NR(chip, pin) \
	((chip << 5) + pin)

/*Get the chip addr from a ioexp gpio*/
#define PORTEXP_IO_TO_CHIP(gpio_nr) \
	(gpio_nr >> 5)

/*Get the pin number from a ioexp gpio*/
#define PORTEXP_IO_TO_PIN(gpio_nr) \
	(gpio_nr & 0x1f)

static int port_exp_direction_output(unsigned gpio, int value)
{
	int ret;

	i2c_set_bus_num(2);
	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
	if (ret)
		return ret;

	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
		(1 << PORTEXP_IO_TO_PIN(gpio)),
		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));

	if (ret)
		return ret;

	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
		(1 << PORTEXP_IO_TO_PIN(gpio)),
		(value << PORTEXP_IO_TO_PIN(gpio)));

	if (ret)
		return ret;

	return 0;
}

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}

#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	gpio_direction_input(IMX_GPIO_NR(6, 15));
	return !gpio_get_value(IMX_GPIO_NR(6, 15));
}

int board_mmc_init(bd_t *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif

#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t gpmi_pads[] = {
	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
	MX6_PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(GPMI_PAD_CTRL1),
};

static void setup_gpmi_nand(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* config gpmi nand iomux */
	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));

	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
	clrbits_le32(&mxc_ccm->CCGR4,
		MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);

	/* config gpmi and bch clock to 100 MHz */
	clrsetbits_le32(&mxc_ccm->cs2cdr,
			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));

	/* enable ENFC_CLK_ROOT clock */
	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);

	/* enable gpmi and bch clock gating */
	setbits_le32(&mxc_ccm->CCGR4,
		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);

	/* enable apbh clock gating */
	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif

int mx6_rgmii_rework(struct phy_device *phydev)
{
	unsigned short val;

	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	setup_iomux_enet();

	return cpu_eth_init(bis);
}

#define BOARD_REV_B  0x200
#define BOARD_REV_A  0x100

static int mx6sabre_rev(void)
{
	/*
	 * Get Board ID information from OCOTP_GP1[15:8]
	 * i.MX6Q ARD RevA: 0x01
	 * i.MX6Q ARD RevB: 0x02
	 */
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;
	int reg = readl(&fuse->gp1);
	int ret;

	switch (reg >> 8 & 0x0F) {
	case 0x02:
		ret = BOARD_REV_B;
		break;
	case 0x01:
	default:
		ret = BOARD_REV_A;
		break;
	}

	return ret;
}

u32 get_board_rev(void)
{
	int rev = mx6sabre_rev();

	return (get_cpu_rev() & ~(0xF << 8)) | rev;
}

#if defined(CONFIG_VIDEO_IPUV3)
static void do_enable_hdmi(struct display_info_t const *dev)
{
	imx_enable_hdmi_phy();
}

struct display_info_t const displays[] = {{
	.bus	= -1,
	.addr	= 0,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.detect	= detect_hdmi,
	.enable	= do_enable_hdmi,
	.mode	= {
		.name           = "HDMI",
		.refresh        = 60,
		.xres           = 1024,
		.yres           = 768,
		.pixclock       = 15385,
		.left_margin    = 220,
		.right_margin   = 40,
		.upper_margin   = 21,
		.lower_margin   = 7,
		.hsync_len      = 60,
		.vsync_len      = 10,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED,
} } };
size_t display_count = ARRAY_SIZE(displays);

static void setup_display(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;

	enable_ipu_clock();
	imx_setup_hdmi();

	reg = readl(&mxc_ccm->chsccdr);
	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif /* CONFIG_VIDEO_IPUV3 */

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

int board_early_init_f(void)
{
	setup_iomux_uart();
#ifdef CONFIG_VIDEO_IPUV3
	setup_display();
#endif

#ifdef CONFIG_NAND_MXS
	setup_gpmi_nand();
#endif
	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	/* I2C 3 Steer */
	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));

	return 0;
}

#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
}
#endif

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{NULL,   0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

	return 0;
}

int checkboard(void)
{
	int rev = mx6sabre_rev();
	char *revname;

	switch (rev) {
	case BOARD_REV_B:
		revname = "B";
		break;
	case BOARD_REV_A:
	default:
		revname = "A";
		break;
	}

	printf("Board: MX6Q-Sabreauto rev%s\n", revname);

	return 0;
}

#ifdef CONFIG_USB_EHCI_MX6
#define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
#define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)

iomux_v3_cfg_t const usb_otg_pads[] = {
	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
};

int board_ehci_hcd_init(int port)
{
	switch (port) {
	case 0:
		imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
			ARRAY_SIZE(usb_otg_pads));

		/*
		  * Set daisy chain for otg_pin_id on 6q.
		 *  For 6dl, this bit is reserved.
		 */
		imx_iomux_set_gpr_register(1, 13, 1, 0);
		break;
	case 1:
		break;
	default:
		printf("MXC USB port %d not yet supported\n", port);
		return -EINVAL;
	}
	return 0;
}

int board_ehci_power(int port, int on)
{
	switch (port) {
	case 0:
		if (on)
			port_exp_direction_output(USB_OTG_PWR, 1);
		else
			port_exp_direction_output(USB_OTG_PWR, 0);
		break;
	case 1:
		if (on)
			port_exp_direction_output(USB_HOST1_PWR, 1);
		else
			port_exp_direction_output(USB_HOST1_PWR, 0);
		break;
	default:
		printf("MXC USB port %d not yet supported\n", port);
		return -EINVAL;
	}

	return 0;
}
#endif
Commit	Line	Data
7dd6545d FE	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
7dd6545d FE	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/clock.h>
	12	#include <asm/arch/imx-regs.h>
	13	#include <asm/arch/iomux.h>
b47abc36	14	#include <asm/arch/mx6-pins.h>
7dd6545d FE	15	#include <asm/errno.h>
	16	#include <asm/gpio.h>
	17	#include <asm/imx-common/iomux-v3.h>
19578165	18	#include <asm/imx-common/mxc_i2c.h>
85449dbd	19	#include <asm/imx-common/boot_mode.h>
3acb011c	20	#include <asm/imx-common/spi.h>
7dd6545d FE	21	#include <mmc.h>
7dd6545d FE	22	#include <fsl_esdhc.h>
fe5ebe97 FE	23	#include <miiphy.h>
fe5ebe97 FE	24	#include <netdev.h>
dce67bd5	25	#include <asm/arch/sys_proto.h>
19578165	26	#include <i2c.h>
510922ac FE	27	#include <asm/arch/mxc_hdmi.h>
	28	#include <asm/imx-common/video.h>
	29	#include <asm/arch/crm_regs.h>
8fe280f3	30	#include <pca953x.h>
dce67bd5	31
7dd6545d FE	32	DECLARE_GLOBAL_DATA_PTR;
7dd6545d FE	33
7e2173cf BT	34	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	35	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	36	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
7dd6545d	37
7e2173cf BT	38	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	39	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	40	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
7dd6545d	41
7e2173cf BT	42	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
7e2173cf BT	43	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
fe5ebe97	44
19578165 RF	45	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	46	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	47	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	48
83bb3215 YL	49	#define GPMI_PAD_CTRL0 (PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_100K_UP)
	50	#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm \| PAD_CTL_SPEED_MED \| \
	51	PAD_CTL_SRE_FAST)
	52	#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 \| GPMI_PAD_CTRL1)
	53
19578165 RF	54	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
19578165 RF	55
7dd6545d FE	56	int dram_init(void)
	57	{
	58	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	59
	60	return 0;
	61	}
	62
067a6593	63	static iomux_v3_cfg_t const uart4_pads[] = {
10fda487 EN	64	MX6_PAD_KEY_COL0__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
10fda487 EN	65	MX6_PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
7dd6545d FE	66	};
7dd6545d FE	67
067a6593	68	static iomux_v3_cfg_t const enet_pads[] = {
cfb8b9d3 EN	69	MX6_PAD_KEY_COL1__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
cfb8b9d3 EN	70	MX6_PAD_KEY_COL2__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
10fda487 EN	71	MX6_PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	72	MX6_PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	73	MX6_PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	74	MX6_PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	75	MX6_PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
cfb8b9d3 EN	76	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
cfb8b9d3 EN	77	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
10fda487 EN	78	MX6_PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	79	MX6_PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	80	MX6_PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	81	MX6_PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	82	MX6_PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
cfb8b9d3	83	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
fe5ebe97 FE	84	};
fe5ebe97 FE	85
19578165	86	/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
067a6593	87	static struct i2c_pads_info i2c_pad_info1 = {
19578165 RF	88	.scl = {
19578165 RF	89	.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL \| PC,
10fda487	90	.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 \| PC,
19578165 RF	91	.gp = IMX_GPIO_NR(2, 30)
	92	},
	93	.sda = {
	94	.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| PC,
10fda487	95	.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 \| PC,
19578165 RF	96	.gp = IMX_GPIO_NR(4, 13)
	97	}
	98	};
	99
	100	/*
	101	* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
	102	* Compass Sensor, Accelerometer, Res Touch
	103	*/
067a6593	104	static struct i2c_pads_info i2c_pad_info2 = {
19578165 RF	105	.scl = {
19578165 RF	106	.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| PC,
10fda487	107	.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 \| PC,
19578165 RF	108	.gp = IMX_GPIO_NR(1, 3)
	109	},
	110	.sda = {
	111	.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA \| PC,
10fda487	112	.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 \| PC,
19578165 RF	113	.gp = IMX_GPIO_NR(3, 18)
	114	}
	115	};
	116
067a6593	117	static iomux_v3_cfg_t const i2c3_pads[] = {
10fda487	118	MX6_PAD_EIM_A24__GPIO5_IO04 \| MUX_PAD_CTRL(NO_PAD_CTRL),
19578165 RF	119	};
19578165 RF	120
067a6593	121	static iomux_v3_cfg_t const port_exp[] = {
10fda487	122	MX6_PAD_SD2_DAT0__GPIO1_IO15 \| MUX_PAD_CTRL(NO_PAD_CTRL),
a1f67807 RF	123	};
a1f67807 RF	124
8fe280f3 YL	125	/Define for building port exp gpio, pin starts from 0/
	126	#define PORTEXP_IO_NR(chip, pin) \
	127	((chip << 5) + pin)
	128
	129	/Get the chip addr from a ioexp gpio/
	130	#define PORTEXP_IO_TO_CHIP(gpio_nr) \
	131	(gpio_nr >> 5)
	132
	133	/Get the pin number from a ioexp gpio/
	134	#define PORTEXP_IO_TO_PIN(gpio_nr) \
	135	(gpio_nr & 0x1f)
	136
	137	static int port_exp_direction_output(unsigned gpio, int value)
	138	{
	139	int ret;
	140
	141	i2c_set_bus_num(2);
	142	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
	143	if (ret)
	144	return ret;
	145
	146	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
	147	(1 << PORTEXP_IO_TO_PIN(gpio)),
	148	(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
	149
	150	if (ret)
	151	return ret;
	152
	153	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
	154	(1 << PORTEXP_IO_TO_PIN(gpio)),
	155	(value << PORTEXP_IO_TO_PIN(gpio)));
	156
	157	if (ret)
	158	return ret;
	159
	160	return 0;
	161	}
	162
fe5ebe97 FE	163	static void setup_iomux_enet(void)
	164	{
	165	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	166	}
	167
067a6593	168	static iomux_v3_cfg_t const usdhc3_pads[] = {
10fda487 EN	169	MX6_PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	170	MX6_PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	171	MX6_PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	172	MX6_PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	173	MX6_PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	174	MX6_PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	175	MX6_PAD_SD3_DAT4__SD3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	176	MX6_PAD_SD3_DAT5__SD3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	177	MX6_PAD_SD3_DAT6__SD3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	178	MX6_PAD_SD3_DAT7__SD3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	179	MX6_PAD_GPIO_18__SD3_VSELECT \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	180	MX6_PAD_NANDF_CS2__GPIO6_IO15 \| MUX_PAD_CTRL(NO_PAD_CTRL),
7dd6545d FE	181	};
	182
	183	static void setup_iomux_uart(void)
	184	{
	185	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
	186	}
	187
	188	#ifdef CONFIG_FSL_ESDHC
067a6593	189	static struct fsl_esdhc_cfg usdhc_cfg[1] = {
7dd6545d FE	190	{USDHC3_BASE_ADDR},
	191	};
	192
	193	int board_mmc_getcd(struct mmc *mmc)
	194	{
	195	gpio_direction_input(IMX_GPIO_NR(6, 15));
	196	return !gpio_get_value(IMX_GPIO_NR(6, 15));
	197	}
	198
	199	int board_mmc_init(bd_t *bis)
	200	{
	201	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	202
a2ac1b3a	203	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
7dd6545d FE	204	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	205	}
	206	#endif
	207
83bb3215 YL	208	#ifdef CONFIG_NAND_MXS
	209	static iomux_v3_cfg_t gpmi_pads[] = {
	210	MX6_PAD_NANDF_CLE__NAND_CLE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	211	MX6_PAD_NANDF_ALE__NAND_ALE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	212	MX6_PAD_NANDF_WP_B__NAND_WP_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	213	MX6_PAD_NANDF_RB0__NAND_READY_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
	214	MX6_PAD_NANDF_CS0__NAND_CE0_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	215	MX6_PAD_SD4_CMD__NAND_RE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	216	MX6_PAD_SD4_CLK__NAND_WE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	217	MX6_PAD_NANDF_D0__NAND_DATA00 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	218	MX6_PAD_NANDF_D1__NAND_DATA01 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	219	MX6_PAD_NANDF_D2__NAND_DATA02 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	220	MX6_PAD_NANDF_D3__NAND_DATA03 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	221	MX6_PAD_NANDF_D4__NAND_DATA04 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	222	MX6_PAD_NANDF_D5__NAND_DATA05 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	223	MX6_PAD_NANDF_D6__NAND_DATA06 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	224	MX6_PAD_NANDF_D7__NAND_DATA07 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	225	MX6_PAD_SD4_DAT0__NAND_DQS \| MUX_PAD_CTRL(GPMI_PAD_CTRL1),
	226	};
	227
	228	static void setup_gpmi_nand(void)
	229	{
	230	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	231
	232	/* config gpmi nand iomux */
	233	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
	234
	235	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
	236	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
	237	clrbits_le32(&mxc_ccm->CCGR4,
	238	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
	239
	240	/* config gpmi and bch clock to 100 MHz */
	241	clrsetbits_le32(&mxc_ccm->cs2cdr,
	242	MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK \|
	243	MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK \|
	244	MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
	245	MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) \|
	246	MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) \|
	247	MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
	248
	249	/* enable ENFC_CLK_ROOT clock */
	250	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
	251
	252	/* enable gpmi and bch clock gating */
	253	setbits_le32(&mxc_ccm->CCGR4,
	254	MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	255	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	256	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	257	MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	258	MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
	259
	260	/* enable apbh clock gating */
	261	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
	262	}
	263	#endif
	264
fe5ebe97 FE	265	int mx6_rgmii_rework(struct phy_device *phydev)
	266	{
	267	unsigned short val;
	268
	269	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	270	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	271	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	272	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	273
	274	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	275	val &= 0xffe3;
	276	val \|= 0x18;
	277	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	278
	279	/* introduce tx clock delay */
	280	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	281	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	282	val \|= 0x0100;
	283	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	284
	285	return 0;
	286	}
	287
	288	int board_phy_config(struct phy_device *phydev)
	289	{
	290	mx6_rgmii_rework(phydev);
	291
	292	if (phydev->drv->config)
	293	phydev->drv->config(phydev);
	294
	295	return 0;
	296	}
	297
	298	int board_eth_init(bd_t *bis)
	299	{
fe5ebe97 FE	300	setup_iomux_enet();
fe5ebe97 FE	301
579be2f7	302	return cpu_eth_init(bis);
fe5ebe97 FE	303	}
fe5ebe97 FE	304
dce67bd5 FE	305	#define BOARD_REV_B 0x200
	306	#define BOARD_REV_A 0x100
	307
	308	static int mx6sabre_rev(void)
	309	{
	310	/*
	311	* Get Board ID information from OCOTP_GP1[15:8]
	312	* i.MX6Q ARD RevA: 0x01
	313	* i.MX6Q ARD RevB: 0x02
	314	*/
	315	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	316	struct fuse_bank *bank = &ocotp->bank[4];
	317	struct fuse_bank4_regs *fuse =
	318	(struct fuse_bank4_regs *)bank->fuse_regs;
	319	int reg = readl(&fuse->gp1);
dce67bd5 FE	320	int ret;
	321
	322	switch (reg >> 8 & 0x0F) {
	323	case 0x02:
	324	ret = BOARD_REV_B;
	325	break;
	326	case 0x01:
	327	default:
	328	ret = BOARD_REV_A;
	329	break;
	330	}
	331
	332	return ret;
	333	}
	334
7dd6545d FE	335	u32 get_board_rev(void)
7dd6545d FE	336	{
dce67bd5 FE	337	int rev = mx6sabre_rev();
	338
	339	return (get_cpu_rev() & ~(0xF << 8)) \| rev;
7dd6545d FE	340	}
7dd6545d FE	341
510922ac FE	342	#if defined(CONFIG_VIDEO_IPUV3)
	343	static void do_enable_hdmi(struct display_info_t const *dev)
	344	{
	345	imx_enable_hdmi_phy();
	346	}
	347
	348	struct display_info_t const displays[] = {{
	349	.bus = -1,
	350	.addr = 0,
	351	.pixfmt = IPU_PIX_FMT_RGB24,
	352	.detect = detect_hdmi,
	353	.enable = do_enable_hdmi,
	354	.mode = {
	355	.name = "HDMI",
	356	.refresh = 60,
	357	.xres = 1024,
	358	.yres = 768,
	359	.pixclock = 15385,
	360	.left_margin = 220,
	361	.right_margin = 40,
	362	.upper_margin = 21,
	363	.lower_margin = 7,
	364	.hsync_len = 60,
	365	.vsync_len = 10,
	366	.sync = FB_SYNC_EXT,
	367	.vmode = FB_VMODE_NONINTERLACED,
	368	} } };
	369	size_t display_count = ARRAY_SIZE(displays);
	370
	371	static void setup_display(void)
	372	{
	373	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	374	int reg;
	375
	376	enable_ipu_clock();
	377	imx_setup_hdmi();
	378
	379	reg = readl(&mxc_ccm->chsccdr);
	380	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
	381	<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	382	writel(reg, &mxc_ccm->chsccdr);
	383	}
	384	#endif /* CONFIG_VIDEO_IPUV3 */
	385
	386	/*
	387	* Do not overwrite the console
	388	* Use always serial for U-Boot console
	389	*/
	390	int overwrite_console(void)
	391	{
	392	return 1;
	393	}
	394
7dd6545d FE	395	int board_early_init_f(void)
	396	{
	397	setup_iomux_uart();
510922ac FE	398	#ifdef CONFIG_VIDEO_IPUV3
	399	setup_display();
	400	#endif
83bb3215 YL	401
	402	#ifdef CONFIG_NAND_MXS
	403	setup_gpmi_nand();
	404	#endif
7dd6545d FE	405	return 0;
	406	}
	407
	408	int board_init(void)
	409	{
	410	/* address of boot parameters */
	411	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	412
19578165 RF	413	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
	414	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	415	/* I2C 3 Steer */
	416	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
	417	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
	418	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	419
a1f67807 RF	420	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
	421	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
	422
7dd6545d FE	423	return 0;
	424	}
	425
155fa9af NK	426	#ifdef CONFIG_MXC_SPI
	427	int board_spi_cs_gpio(unsigned bus, unsigned cs)
	428	{
	429	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
	430	}
	431	#endif
	432
85449dbd OS	433	#ifdef CONFIG_CMD_BMODE
	434	static const struct boot_mode board_boot_modes[] = {
	435	/* 4 bit bus width */
	436	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	437	{NULL, 0},
	438	};
	439	#endif
	440
	441	int board_late_init(void)
	442	{
	443	#ifdef CONFIG_CMD_BMODE
	444	add_board_boot_modes(board_boot_modes);
	445	#endif
	446
	447	return 0;
	448	}
	449
7dd6545d FE	450	int checkboard(void)
7dd6545d FE	451	{
dce67bd5 FE	452	int rev = mx6sabre_rev();
	453	char *revname;
	454
	455	switch (rev) {
	456	case BOARD_REV_B:
	457	revname = "B";
	458	break;
	459	case BOARD_REV_A:
	460	default:
	461	revname = "A";
	462	break;
	463	}
	464
	465	printf("Board: MX6Q-Sabreauto rev%s\n", revname);
7dd6545d FE	466
	467	return 0;
	468	}
8fe280f3 YL	469
	470	#ifdef CONFIG_USB_EHCI_MX6
	471	#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
	472	#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
	473
	474	iomux_v3_cfg_t const usb_otg_pads[] = {
	475	MX6_PAD_ENET_RX_ER__USB_OTG_ID \| MUX_PAD_CTRL(NO_PAD_CTRL),
	476	};
	477
	478	int board_ehci_hcd_init(int port)
	479	{
	480	switch (port) {
	481	case 0:
	482	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
	483	ARRAY_SIZE(usb_otg_pads));
	484
	485	/*
	486	* Set daisy chain for otg_pin_id on 6q.
	487	* For 6dl, this bit is reserved.
	488	*/
	489	imx_iomux_set_gpr_register(1, 13, 1, 0);
	490	break;
	491	case 1:
	492	break;
	493	default:
	494	printf("MXC USB port %d not yet supported\n", port);
	495	return -EINVAL;
	496	}
	497	return 0;
	498	}
	499
	500	int board_ehci_power(int port, int on)
	501	{
	502	switch (port) {
	503	case 0:
	504	if (on)
	505	port_exp_direction_output(USB_OTG_PWR, 1);
	506	else
	507	port_exp_direction_output(USB_OTG_PWR, 0);
	508	break;
	509	case 1:
	510	if (on)
	511	port_exp_direction_output(USB_HOST1_PWR, 1);
	512	else
	513	port_exp_direction_output(USB_HOST1_PWR, 0);
	514	break;
	515	default:
	516	printf("MXC USB port %d not yet supported\n", port);
	517	return -EINVAL;
	518	}
	519
	520	return 0;
	521	}
	522	#endif