[people/ms/u-boot.git] / board / freescale / mx6qsabresd / mx6qsabresd.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

iomux_v3_cfg_t const uart1_pads[] = {
	MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

iomux_v3_cfg_t const enet_pads[] = {
	MX6Q_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
	/* AR8031 PHY Reset */
	MX6Q_PAD_ENET_CRS_DV__GPIO_1_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

	/* Reset AR8031 PHY */
	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
	udelay(500);
	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}

iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6Q_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC3_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	gpio_direction_input(IMX_GPIO_NR(2, 0));
	return !gpio_get_value(IMX_GPIO_NR(2, 0));
}

int board_mmc_init(bd_t *bis)
{
	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif

int mx6_rgmii_rework(struct phy_device *phydev)
{
	unsigned short val;

	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int ret;

	setup_iomux_enet();

	ret = cpu_eth_init(bis);
	if (ret)
		printf("FEC MXC: %s:failed\n", __func__);

	return 0;
}

u32 get_board_rev(void)
{
	return 0x63000;
}

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	return 0;
}

int checkboard(void)
{
	puts("Board: MX6Q-SabreSD\n");

	return 0;
}
Commit	Line	Data
7891e258 FE	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*/
	19
	20	#include <common.h>
	21	#include <asm/io.h>
	22	#include <asm/arch/clock.h>
	23	#include <asm/arch/imx-regs.h>
	24	#include <asm/arch/iomux.h>
	25	#include <asm/arch/mx6x_pins.h>
	26	#include <asm/errno.h>
	27	#include <asm/gpio.h>
	28	#include <asm/imx-common/iomux-v3.h>
	29	#include <mmc.h>
	30	#include <fsl_esdhc.h>
	31	#include <miiphy.h>
	32	#include <netdev.h>
	33	DECLARE_GLOBAL_DATA_PTR;
	34
	35	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	36	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	37	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	38
	39	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	40	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	41	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	42
	43	#define ENET_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	44	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	45	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	46
	47	int dram_init(void)
	48	{
	49	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	50
	51	return 0;
	52	}
	53
6e142320	54	iomux_v3_cfg_t const uart1_pads[] = {
7891e258 FE	55	MX6Q_PAD_CSI0_DAT10__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	56	MX6Q_PAD_CSI0_DAT11__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	57	};
	58
6e142320	59	iomux_v3_cfg_t const enet_pads[] = {
a0d21fc0 FE	60	MX6Q_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	61	MX6Q_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	62	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	63	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	64	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	65	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	66	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	67	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	68	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	69	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	70	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	71	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	72	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	73	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	74	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	75	/* AR8031 PHY Reset */
	76	MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	77	};
	78
	79	static void setup_iomux_enet(void)
	80	{
	81	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	82
	83	/* Reset AR8031 PHY */
	84	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
	85	udelay(500);
	86	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
	87	}
	88
6e142320	89	iomux_v3_cfg_t const usdhc3_pads[] = {
7891e258 FE	90	MX6Q_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	91	MX6Q_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	92	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	93	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	94	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	95	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
e72d6178 FE	96	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	97	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	98	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	99	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
7891e258 FE	100	MX6Q_PAD_NANDF_D0__GPIO_2_0 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
	101	};
	102
	103	static void setup_iomux_uart(void)
	104	{
	105	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	106	}
	107
	108	#ifdef CONFIG_FSL_ESDHC
	109	struct fsl_esdhc_cfg usdhc_cfg[1] = {
	110	{USDHC3_BASE_ADDR},
	111	};
	112
	113	int board_mmc_getcd(struct mmc *mmc)
	114	{
	115	gpio_direction_input(IMX_GPIO_NR(2, 0));
	116	return !gpio_get_value(IMX_GPIO_NR(2, 0));
	117	}
	118
	119	int board_mmc_init(bd_t *bis)
	120	{
	121	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	122
a2ac1b3a	123	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
7891e258 FE	124	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	125	}
	126	#endif
	127
a0d21fc0 FE	128	int mx6_rgmii_rework(struct phy_device *phydev)
	129	{
	130	unsigned short val;
	131
	132	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	133	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	134	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	135	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	136
	137	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	138	val &= 0xffe3;
	139	val \|= 0x18;
	140	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	141
	142	/* introduce tx clock delay */
	143	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	144	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	145	val \|= 0x0100;
	146	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	147
	148	return 0;
	149	}
	150
	151	int board_phy_config(struct phy_device *phydev)
	152	{
	153	mx6_rgmii_rework(phydev);
	154
	155	if (phydev->drv->config)
	156	phydev->drv->config(phydev);
	157
	158	return 0;
	159	}
	160
	161	int board_eth_init(bd_t *bis)
	162	{
	163	int ret;
	164
	165	setup_iomux_enet();
	166
	167	ret = cpu_eth_init(bis);
	168	if (ret)
	169	printf("FEC MXC: %s:failed\n", __func__);
	170
	171	return 0;
	172	}
	173
7891e258 FE	174	u32 get_board_rev(void)
	175	{
	176	return 0x63000;
	177	}
	178
	179	int board_early_init_f(void)
	180	{
	181	setup_iomux_uart();
	182
	183	return 0;
	184	}
	185
	186	int board_init(void)
	187	{
	188	/* address of boot parameters */
	189	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	190
	191	return 0;
	192	}
	193
	194	int checkboard(void)
	195	{
	196	puts("Board: MX6Q-SabreSD\n");
	197
	198	return 0;
	199	}