[thirdparty/u-boot.git] / board / freescale / mx6slevk / mx6slevk.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 */

#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)

#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
			PAD_CTL_SRE_FAST)

#define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};

#ifdef CONFIG_SPL_BUILD
static iomux_v3_cfg_t const usdhc1_pads[] = {
	/* 8 bit SD */
	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/*CD pin*/
	MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/*CD pin*/
	MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/*CD pin*/
	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#endif

static iomux_v3_cfg_t const fec_pads[] = {
	MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

#ifdef CONFIG_MXC_SPI
static iomux_v3_cfg_t ecspi1_pads[] = {
	MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
};

int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
}

static void setup_spi(void)
{
	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

static void setup_iomux_fec(void)
{
	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));

	/* Power up LAN8720 PHY */
	gpio_request(ETH_PHY_POWER, "eth_pwr");
	gpio_direction_output(ETH_PHY_POWER , 1);
	udelay(15000);
}

int board_mmc_get_env_dev(int devno)
{
	return devno;
}

#ifdef CONFIG_DM_PMIC_PFUZE100
int power_init_board(void)
{
	struct udevice *dev;
	int ret;
	u32 dev_id, rev_id, i;
	u32 switch_num = 6;
	u32 offset = PFUZE100_SW1CMODE;

	ret = pmic_get("pfuze100", &dev);
	if (ret == -ENODEV)
		return 0;

	if (ret != 0)
		return ret;

	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);

	/* set SW1AB staby volatage 0.975V */
	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);

	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);

	/* set SW1C staby volatage 0.975V */
	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);

	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);

	/* Init mode to APS_PFM */
	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);

	for (i = 0; i < switch_num - 1; i++)
		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);

	return 0;
}
#endif

#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
	setup_iomux_fec();

	return cpu_eth_init(bis);
}

static int setup_fec(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);

	return enable_fec_anatop_clock(0, ENET_50MHZ);
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_MXC_SPI
	gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
	setup_spi();
#endif

#ifdef	CONFIG_FEC_MXC
	setup_fec();
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: MX6SLEVK\n");

	return 0;
}

#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#include <linux/libfdt.h>

#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)

static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC1_BASE_ADDR},
	{USDHC2_BASE_ADDR, 0, 4},
	{USDHC3_BASE_ADDR, 0, 4},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC2_BASE_ADDR:
		gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
		ret = !gpio_get_value(USDHC3_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
	u32 val;
	u32 port;

	val = readl(&src_regs->sbmr1);

	/* Boot from USDHC */
	port = (val >> 11) & 0x3;
	switch (port) {
	case 0:
		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
						 ARRAY_SIZE(usdhc1_pads));
		gpio_direction_input(USDHC1_CD_GPIO);
		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
		break;
	case 1:
		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
						 ARRAY_SIZE(usdhc2_pads));
		gpio_direction_input(USDHC2_CD_GPIO);
		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
		usdhc_cfg[0].max_bus_width = 4;
		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
		break;
	case 2:
		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
						 ARRAY_SIZE(usdhc3_pads));
		gpio_direction_input(USDHC3_CD_GPIO);
		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
		usdhc_cfg[0].max_bus_width = 4;
		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
		break;
	}

	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}

const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_sdqs0 = 0x00003030,
	.dram_sdqs1 = 0x00003030,
	.dram_sdqs2 = 0x00003030,
	.dram_sdqs3 = 0x00003030,
	.dram_dqm0 = 0x00000030,
	.dram_dqm1 = 0x00000030,
	.dram_dqm2 = 0x00000030,
	.dram_dqm3 = 0x00000030,
	.dram_cas  = 0x00000030,
	.dram_ras  = 0x00000030,
	.dram_sdclk_0 = 0x00000028,
	.dram_reset = 0x00000030,
	.dram_sdba2 = 0x00000000,
	.dram_odt0 = 0x00000008,
	.dram_odt1 = 0x00000008,
};

const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_addds = 0x00000030,
	.grp_ctlds = 0x00000030,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
	.grp_ddr_type = 0x00080000,
};

const struct mx6_mmdc_calibration mx6_mmcd_calib = {
	.p0_mpdgctrl0 =  0x20000000,
	.p0_mpdgctrl1 =  0x00000000,
	.p0_mprddlctl =  0x4241444a,
	.p0_mpwrdlctl =  0x3030312b,
	.mpzqlp2ctl = 0x1b4700c7,
};

static struct mx6_lpddr2_cfg mem_ddr = {
	.mem_speed = 800,
	.density = 4,
	.width = 32,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.trcd_lp = 2000,
	.trppb_lp = 2000,
	.trpab_lp = 2250,
	.trasmin = 4200,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0xFFFFFFFF, &ccm->CCGR0);
	writel(0xFFFFFFFF, &ccm->CCGR1);
	writel(0xFFFFFFFF, &ccm->CCGR2);
	writel(0xFFFFFFFF, &ccm->CCGR3);
	writel(0xFFFFFFFF, &ccm->CCGR4);
	writel(0xFFFFFFFF, &ccm->CCGR5);
	writel(0xFFFFFFFF, &ccm->CCGR6);

	writel(0x00260324, &ccm->cbcmr);
}

static void spl_dram_init(void)
{
	struct mx6_ddr_sysinfo sysinfo = {
		.dsize = mem_ddr.width / 32,
		.cs_density = 20,
		.ncs = 2,
		.cs1_mirror = 0,
		.walat = 0,
		.ralat = 2,
		.mif3_mode = 3,
		.bi_on = 1,
		.rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
		.rtt_nom = 0,
		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
		.ddr_type = DDR_TYPE_LPDDR2,
		.refsel = 0,	/* Refresh cycles at 64KHz */
		.refr = 3,	/* 4 refresh commands per refresh cycle */
	};
	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}

void board_init_f(ulong dummy)
{
	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();

	/* iomux and setup of i2c */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
57ca432f FE	2	/*
	3	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	4	*
	5	* Author: Fabio Estevam <fabio.estevam@freescale.com>
57ca432f FE	6	*/
	7
	8	#include <asm/arch/clock.h>
	9	#include <asm/arch/iomux.h>
e7d3b21b	10	#include <asm/arch/crm_regs.h>
57ca432f	11	#include <asm/arch/imx-regs.h>
e7d3b21b	12	#include <asm/arch/mx6-ddr.h>
57ca432f FE	13	#include <asm/arch/mx6-pins.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/gpio.h>
552a848e SB	16	#include <asm/mach-imx/iomux-v3.h>
	17	#include <asm/mach-imx/mxc_i2c.h>
	18	#include <asm/mach-imx/spi.h>
57ca432f	19	#include <asm/io.h>
1ace4022	20	#include <linux/sizes.h>
57ca432f	21	#include <common.h>
e37ac717	22	#include <fsl_esdhc_imx.h>
af38bf6b	23	#include <i2c.h>
57ca432f	24	#include <mmc.h>
31f07964	25	#include <netdev.h>
af38bf6b PF	26	#include <power/pmic.h>
	27	#include <power/pfuze100_pmic.h>
	28	#include "../common/pfuze.h"
57ca432f FE	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
7e2173cf BT	32	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	33	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	34	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
57ca432f	35
7e2173cf BT	36	#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP \| \
	37	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	38	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
57ca432f	39
31f07964 FE	40	#define ENET_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	41	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	42	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	43
694c3bc1 FE	44	#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	45	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	46
16edd347 FE	47	#define OTGID_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	48	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \|\
	49	PAD_CTL_DSE_80ohm \| PAD_CTL_HYS \| \
	50	PAD_CTL_SRE_FAST)
	51
ae765f3a	52	#define ETH_PHY_POWER IMX_GPIO_NR(4, 21)
31f07964	53
57ca432f FE	54	int dram_init(void)
57ca432f FE	55	{
8259e9c9	56	gd->ram_size = imx_ddr_size();
57ca432f FE	57
	58	return 0;
	59	}
	60
	61	static iomux_v3_cfg_t const uart1_pads[] = {
	62	MX6_PAD_UART1_TXD__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	63	MX6_PAD_UART1_RXD__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	64	};
	65
61ebeb99	66	#ifdef CONFIG_SPL_BUILD
36255d67 YL	67	static iomux_v3_cfg_t const usdhc1_pads[] = {
	68	/* 8 bit SD */
	69	MX6_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	70	MX6_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	71	MX6_PAD_SD1_DAT0__USDHC1_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	72	MX6_PAD_SD1_DAT1__USDHC1_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	73	MX6_PAD_SD1_DAT2__USDHC1_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	74	MX6_PAD_SD1_DAT3__USDHC1_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	75	MX6_PAD_SD1_DAT4__USDHC1_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	76	MX6_PAD_SD1_DAT5__USDHC1_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	77	MX6_PAD_SD1_DAT6__USDHC1_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	78	MX6_PAD_SD1_DAT7__USDHC1_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	79
	80	/CD pin/
	81	MX6_PAD_KEY_ROW7__GPIO_4_7 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	82	};
	83
57ca432f FE	84	static iomux_v3_cfg_t const usdhc2_pads[] = {
	85	MX6_PAD_SD2_CLK__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	86	MX6_PAD_SD2_CMD__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	87	MX6_PAD_SD2_DAT0__USDHC2_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	88	MX6_PAD_SD2_DAT1__USDHC2_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	89	MX6_PAD_SD2_DAT2__USDHC2_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	90	MX6_PAD_SD2_DAT3__USDHC2_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
36255d67 YL	91
	92	/CD pin/
	93	MX6_PAD_SD2_DAT7__GPIO_5_0 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	94	};
	95
	96	static iomux_v3_cfg_t const usdhc3_pads[] = {
	97	MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	98	MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	99	MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	100	MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	101	MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	102	MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	103
	104	/CD pin/
	105	MX6_PAD_REF_CLK_32K__GPIO_3_22 \| MUX_PAD_CTRL(NO_PAD_CTRL),
57ca432f	106	};
61ebeb99	107	#endif
57ca432f	108
31f07964 FE	109	static iomux_v3_cfg_t const fec_pads[] = {
	110	MX6_PAD_FEC_MDC__FEC_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	111	MX6_PAD_FEC_MDIO__FEC_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	112	MX6_PAD_FEC_CRS_DV__FEC_RX_DV \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	113	MX6_PAD_FEC_RXD0__FEC_RX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	114	MX6_PAD_FEC_RXD1__FEC_RX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	115	MX6_PAD_FEC_TX_EN__FEC_TX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	116	MX6_PAD_FEC_TXD0__FEC_TX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	117	MX6_PAD_FEC_TXD1__FEC_TX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	118	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	119	MX6_PAD_FEC_RX_ER__GPIO_4_19 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	120	MX6_PAD_FEC_TX_CLK__GPIO_4_21 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	121	};
	122
694c3bc1 FE	123	#ifdef CONFIG_MXC_SPI
	124	static iomux_v3_cfg_t ecspi1_pads[] = {
	125	MX6_PAD_ECSPI1_MISO__ECSPI_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	126	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	127	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	128	MX6_PAD_ECSPI1_SS0__GPIO4_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	129	};
	130
155fa9af NK	131	int board_spi_cs_gpio(unsigned bus, unsigned cs)
	132	{
	133	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
	134	}
	135
694c3bc1 FE	136	static void setup_spi(void)
	137	{
	138	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
	139	}
	140	#endif
	141
57ca432f FE	142	static void setup_iomux_uart(void)
	143	{
	144	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	145	}
	146
31f07964 FE	147	static void setup_iomux_fec(void)
	148	{
	149	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
	150
ae765f3a	151	/* Power up LAN8720 PHY */
001cdbbb	152	gpio_request(ETH_PHY_POWER, "eth_pwr");
ae765f3a FE	153	gpio_direction_output(ETH_PHY_POWER , 1);
ae765f3a FE	154	udelay(15000);
31f07964 FE	155	}
31f07964 FE	156
fb0d0428 PF	157	int board_mmc_get_env_dev(int devno)
	158	{
	159	return devno;
	160	}
	161
001cdbbb PF	162	#ifdef CONFIG_DM_PMIC_PFUZE100
001cdbbb PF	163	int power_init_board(void)
57ca432f	164	{
001cdbbb PF	165	struct udevice *dev;
	166	int ret;
	167	u32 dev_id, rev_id, i;
	168	u32 switch_num = 6;
	169	u32 offset = PFUZE100_SW1CMODE;
36255d67	170
001cdbbb PF	171	ret = pmic_get("pfuze100", &dev);
	172	if (ret == -ENODEV)
	173	return 0;
57ca432f	174
001cdbbb PF	175	if (ret != 0)
001cdbbb PF	176	return ret;
57ca432f	177
001cdbbb PF	178	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
	179	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
	180	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
e7d3b21b	181
001cdbbb PF	182	/* set SW1AB staby volatage 0.975V */
001cdbbb PF	183	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
e7d3b21b	184
001cdbbb PF	185	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
001cdbbb PF	186	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
e7d3b21b	187
001cdbbb PF	188	/* set SW1C staby volatage 0.975V */
001cdbbb PF	189	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
57ca432f	190
001cdbbb PF	191	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
001cdbbb PF	192	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
af38bf6b	193
001cdbbb PF	194	/* Init mode to APS_PFM */
001cdbbb PF	195	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
af38bf6b	196
001cdbbb PF	197	for (i = 0; i < switch_num - 1; i++)
001cdbbb PF	198	pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
af38bf6b	199
001cdbbb	200	return 0;
af38bf6b PF	201	}
	202	#endif
	203
31f07964 FE	204	#ifdef CONFIG_FEC_MXC
	205	int board_eth_init(bd_t *bis)
	206	{
31f07964 FE	207	setup_iomux_fec();
31f07964 FE	208
12c20c0c	209	return cpu_eth_init(bis);
31f07964 FE	210	}
	211
	212	static int setup_fec(void)
	213	{
0a11d6f2	214	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
31f07964 FE	215
	216	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
	217	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
	218
6d97dc10	219	return enable_fec_anatop_clock(0, ENET_50MHZ);
31f07964 FE	220	}
	221	#endif
	222
57ca432f FE	223	int board_early_init_f(void)
	224	{
	225	setup_iomux_uart();
001cdbbb	226
57ca432f FE	227	return 0;
	228	}
	229
	230	int board_init(void)
	231	{
	232	/* address of boot parameters */
	233	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	234
001cdbbb PF	235	#ifdef CONFIG_MXC_SPI
	236	gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
	237	setup_spi();
af38bf6b PF	238	#endif
af38bf6b PF	239
31f07964 FE	240	#ifdef CONFIG_FEC_MXC
	241	setup_fec();
	242	#endif
3b9c1a5d	243
57ca432f FE	244	return 0;
	245	}
	246
57ca432f FE	247	int checkboard(void)
	248	{
	249	puts("Board: MX6SLEVK\n");
	250
	251	return 0;
	252	}
e7d3b21b PF	253
	254	#ifdef CONFIG_SPL_BUILD
	255	#include <spl.h>
b08c8c48	256	#include <linux/libfdt.h>
e7d3b21b	257
001cdbbb PF	258	#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
	259	#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
	260	#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
	261
	262	static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	263	{USDHC1_BASE_ADDR},
	264	{USDHC2_BASE_ADDR, 0, 4},
	265	{USDHC3_BASE_ADDR, 0, 4},
	266	};
	267
	268	int board_mmc_getcd(struct mmc *mmc)
	269	{
	270	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	271	int ret = 0;
	272
	273	switch (cfg->esdhc_base) {
	274	case USDHC1_BASE_ADDR:
40b0dae1	275	gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
001cdbbb PF	276	ret = !gpio_get_value(USDHC1_CD_GPIO);
	277	break;
	278	case USDHC2_BASE_ADDR:
40b0dae1	279	gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
001cdbbb PF	280	ret = !gpio_get_value(USDHC2_CD_GPIO);
	281	break;
	282	case USDHC3_BASE_ADDR:
40b0dae1	283	gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
001cdbbb PF	284	ret = !gpio_get_value(USDHC3_CD_GPIO);
	285	break;
	286	}
	287
	288	return ret;
	289	}
	290
	291	int board_mmc_init(bd_t *bis)
	292	{
	293	struct src src_regs = (struct src )SRC_BASE_ADDR;
	294	u32 val;
	295	u32 port;
	296
	297	val = readl(&src_regs->sbmr1);
	298
	299	/* Boot from USDHC */
	300	port = (val >> 11) & 0x3;
	301	switch (port) {
	302	case 0:
	303	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
	304	ARRAY_SIZE(usdhc1_pads));
	305	gpio_direction_input(USDHC1_CD_GPIO);
	306	usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
	307	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	308	break;
	309	case 1:
	310	imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
	311	ARRAY_SIZE(usdhc2_pads));
	312	gpio_direction_input(USDHC2_CD_GPIO);
	313	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
	314	usdhc_cfg[0].max_bus_width = 4;
	315	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	316	break;
	317	case 2:
	318	imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
	319	ARRAY_SIZE(usdhc3_pads));
	320	gpio_direction_input(USDHC3_CD_GPIO);
	321	usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
	322	usdhc_cfg[0].max_bus_width = 4;
	323	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	324	break;
	325	}
	326
	327	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
	328	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	329	}
	330
e7d3b21b PF	331	const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
	332	.dram_sdqs0 = 0x00003030,
	333	.dram_sdqs1 = 0x00003030,
	334	.dram_sdqs2 = 0x00003030,
	335	.dram_sdqs3 = 0x00003030,
	336	.dram_dqm0 = 0x00000030,
	337	.dram_dqm1 = 0x00000030,
	338	.dram_dqm2 = 0x00000030,
	339	.dram_dqm3 = 0x00000030,
	340	.dram_cas = 0x00000030,
	341	.dram_ras = 0x00000030,
	342	.dram_sdclk_0 = 0x00000028,
	343	.dram_reset = 0x00000030,
	344	.dram_sdba2 = 0x00000000,
	345	.dram_odt0 = 0x00000008,
	346	.dram_odt1 = 0x00000008,
	347	};
	348
	349	const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
	350	.grp_b0ds = 0x00000030,
	351	.grp_b1ds = 0x00000030,
	352	.grp_b2ds = 0x00000030,
	353	.grp_b3ds = 0x00000030,
	354	.grp_addds = 0x00000030,
	355	.grp_ctlds = 0x00000030,
	356	.grp_ddrmode_ctl = 0x00020000,
	357	.grp_ddrpke = 0x00000000,
	358	.grp_ddrmode = 0x00020000,
	359	.grp_ddr_type = 0x00080000,
	360	};
	361
	362	const struct mx6_mmdc_calibration mx6_mmcd_calib = {
	363	.p0_mpdgctrl0 = 0x20000000,
	364	.p0_mpdgctrl1 = 0x00000000,
	365	.p0_mprddlctl = 0x4241444a,
	366	.p0_mpwrdlctl = 0x3030312b,
	367	.mpzqlp2ctl = 0x1b4700c7,
	368	};
	369
	370	static struct mx6_lpddr2_cfg mem_ddr = {
	371	.mem_speed = 800,
	372	.density = 4,
	373	.width = 32,
	374	.banks = 8,
	375	.rowaddr = 14,
	376	.coladdr = 10,
	377	.trcd_lp = 2000,
	378	.trppb_lp = 2000,
	379	.trpab_lp = 2250,
	380	.trasmin = 4200,
	381	};
	382
	383	static void ccgr_init(void)
	384	{
	385	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	386
	387	writel(0xFFFFFFFF, &ccm->CCGR0);
	388	writel(0xFFFFFFFF, &ccm->CCGR1);
	389	writel(0xFFFFFFFF, &ccm->CCGR2);
	390	writel(0xFFFFFFFF, &ccm->CCGR3);
	391	writel(0xFFFFFFFF, &ccm->CCGR4);
	392	writel(0xFFFFFFFF, &ccm->CCGR5);
	393	writel(0xFFFFFFFF, &ccm->CCGR6);
	394
395	writel(0x00260324, &ccm->cbcmr);
396	}
397
398	static void spl_dram_init(void)
399	{
400	struct mx6_ddr_sysinfo sysinfo = {
401	.dsize = mem_ddr.width / 32,
402	.cs_density = 20,
403	.ncs = 2,
404	.cs1_mirror = 0,
405	.walat = 0,
406	.ralat = 2,
407	.mif3_mode = 3,
408	.bi_on = 1,
409	.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
410	.rtt_nom = 0,
411	.sde_to_rst = 0, /* LPDDR2 does not need this field */
412	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
413	.ddr_type = DDR_TYPE_LPDDR2,
edf00937 FE	414	.refsel = 0, /* Refresh cycles at 64KHz */
edf00937 FE	415	.refr = 3, /* 4 refresh commands per refresh cycle */
e7d3b21b PF	416	};
	417	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	418	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
	419	}
	420
	421	void board_init_f(ulong dummy)
	422	{
	423	/* setup AIPS and disable watchdog */
	424	arch_cpu_init();
	425
	426	ccgr_init();
	427
	428	/* iomux and setup of i2c */
	429	board_early_init_f();
	430
	431	/* setup GP timer */
	432	timer_init();
	433
	434	/* UART clocks enabled and gd valid - init serial console */
	435	preloader_console_init();
	436
	437	/* DDR initialization */
	438	spl_dram_init();
	439
	440	/* Clear the BSS. */
	441	memset(__bss_start, 0, __bss_end - __bss_start);
	442
	443	/* load/boot image from boot device */
	444	board_init_r(NULL, 0);
	445	}
e7d3b21b	446	#endif