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mx6ul_14x14_evk: Staticize when possible
[people/ms/u-boot.git] / board / freescale / mx6ul_14x14_evk / mx6ul_14x14_evk.c
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f0ff57b0
PF		 1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/mx6ul_pins.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/gpio.h>
15#include <asm/imx-common/iomux-v3.h>
16#include <asm/imx-common/boot_mode.h>
17#include <asm/imx-common/mxc_i2c.h>
18#include <asm/io.h>
19#include <common.h>
20#include <fsl_esdhc.h>
21#include <i2c.h>
0d4cdb56 22#include <miiphy.h>
f0ff57b0
PF		 23#include <linux/sizes.h>
24#include <mmc.h>
0d4cdb56 25#include <netdev.h>
d9cbb264
PF		 26#include <power/pmic.h>
27#include <power/pfuze3000_pmic.h>
28#include "../common/pfuze.h"
f0ff57b0
PF		 29#include <usb.h>
30#include <usb/ehci-fsl.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE)
50
0d4cdb56
PF		 51#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
54
55#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
57
58#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
59
60#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
61 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
62
f0ff57b0
PF		 63#define IOX_SDI IMX_GPIO_NR(5, 10)
64#define IOX_STCP IMX_GPIO_NR(5, 7)
65#define IOX_SHCP IMX_GPIO_NR(5, 11)
66#define IOX_OE IMX_GPIO_NR(5, 18)
67
68static iomux_v3_cfg_t const iox_pads[] = {
69 /* IOX_SDI */
70 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
71 /* IOX_SHCP */
72 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
73 /* IOX_STCP */
74 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
75 /* IOX_nOE */
76 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
77};
78
79/*
80 * HDMI_nRST --> Q0
81 * ENET1_nRST --> Q1
82 * ENET2_nRST --> Q2
83 * CAN1_2_STBY --> Q3
84 * BT_nPWD --> Q4
85 * CSI_RST --> Q5
86 * CSI_PWDN --> Q6
87 * LCD_nPWREN --> Q7
88 */
89enum qn {
90 HDMI_NRST,
91 ENET1_NRST,
92 ENET2_NRST,
93 CAN1_2_STBY,
94 BT_NPWD,
95 CSI_RST,
96 CSI_PWDN,
97 LCD_NPWREN,
98};
99
100enum qn_func {
101 qn_reset,
102 qn_enable,
103 qn_disable,
104};
105
106enum qn_level {
107 qn_low = 0,
108 qn_high = 1,
109};
110
111static enum qn_level seq[3][2] = {
112 {0, 1}, {1, 1}, {0, 0}
113};
114
115static enum qn_func qn_output[8] = {
116 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
117 qn_disable, qn_enable
118};
119
120static void iox74lv_init(void)
121{
122 int i;
123
124 gpio_direction_output(IOX_OE, 0);
125
126 for (i = 7; i >= 0; i--) {
127 gpio_direction_output(IOX_SHCP, 0);
128 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
129 udelay(500);
130 gpio_direction_output(IOX_SHCP, 1);
131 udelay(500);
132 }
133
134 gpio_direction_output(IOX_STCP, 0);
135 udelay(500);
136 /*
137 * shift register will be output to pins
138 */
139 gpio_direction_output(IOX_STCP, 1);
140
141 for (i = 7; i >= 0; i--) {
142 gpio_direction_output(IOX_SHCP, 0);
143 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
144 udelay(500);
145 gpio_direction_output(IOX_SHCP, 1);
146 udelay(500);
147 }
148 gpio_direction_output(IOX_STCP, 0);
149 udelay(500);
150 /*
151 * shift register will be output to pins
152 */
153 gpio_direction_output(IOX_STCP, 1);
154
155 gpio_direction_output(IOX_OE, 1);
156};
157
f0ff57b0
PF		 158#ifdef CONFIG_SYS_I2C_MXC
159#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
160/* I2C1 for PMIC and EEPROM */
d547e7ab 161static struct i2c_pads_info i2c_pad_info1 = {
f0ff57b0
PF		 162 .scl = {
163 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
164 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
165 .gp = IMX_GPIO_NR(1, 28),
166 },
167 .sda = {
168 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
169 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
170 .gp = IMX_GPIO_NR(1, 29),
171 },
172};
d9cbb264
PF		 173
174#ifdef CONFIG_POWER
175#define I2C_PMIC 0
176int power_init_board(void)
177{
178 if (is_mx6ul_9x9_evk()) {
179 struct pmic *pfuze;
180 int ret;
181 unsigned int reg, rev_id;
182
183 ret = power_pfuze3000_init(I2C_PMIC);
184 if (ret)
185 return ret;
186
187 pfuze = pmic_get("PFUZE3000");
188 ret = pmic_probe(pfuze);
189 if (ret)
190 return ret;
191
192 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
193 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
194 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
195 reg, rev_id);
196
197 /* disable Low Power Mode during standby mode */
198 pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
199 reg |= 0x1;
200 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
201
202 /* SW1B step ramp up time from 2us to 4us/25mV */
203 reg = 0x40;
204 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
205
206 /* SW1B mode to APS/PFM */
207 reg = 0xc;
208 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
209
210 /* SW1B standby voltage set to 0.975V */
211 reg = 0xb;
212 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
213 }
214
215 return 0;
216}
217#endif
f0ff57b0
PF		 218#endif
219
220int dram_init(void)
221{
d9cbb264 222 gd->ram_size = imx_ddr_size();
f0ff57b0
PF		 223
224 return 0;
225}
226
227static iomux_v3_cfg_t const uart1_pads[] = {
228 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
229 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
230};
231
232static iomux_v3_cfg_t const usdhc1_pads[] = {
233 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
234 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
235 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
236 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
237 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
238 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
239
240 /* VSELECT */
241 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
242 /* CD */
243 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
244 /* RST_B */
245 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
246};
247
248/*
249 * mx6ul_14x14_evk board default supports sd card. If want to use
250 * EMMC, need to do board rework for sd2.
251 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
252 * emmc, need to define this macro.
253 */
254#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
255static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
256 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
261 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
262 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
263 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
264 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
265 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
266
267 /*
268 * RST_B
269 */
270 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
271};
272#else
273static iomux_v3_cfg_t const usdhc2_pads[] = {
274 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
275 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
276 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
277 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
278 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
279 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
280};
281
282static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
283 /*
284 * The evk board uses DAT3 to detect CD card plugin,
285 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
286 */
287 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
288};
289
290static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
291 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
292 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
293};
294#endif
295
296static void setup_iomux_uart(void)
297{
298 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
299}
300
301#ifdef CONFIG_FSL_QSPI
302
303#define QSPI_PAD_CTRL1 \
304 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
305 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
306
307static iomux_v3_cfg_t const quadspi_pads[] = {
308 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
309 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
310 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
311 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
312 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
313 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
314};
315
d547e7ab 316static int board_qspi_init(void)
f0ff57b0
PF		 317{
318 /* Set the iomux */
319 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
320 ARRAY_SIZE(quadspi_pads));
321 /* Set the clock */
322 enable_qspi_clk(0);
323
324 return 0;
325}
326#endif
327
328#ifdef CONFIG_FSL_ESDHC
329static struct fsl_esdhc_cfg usdhc_cfg[2] = {
330 {USDHC1_BASE_ADDR, 0, 4},
331#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
332 {USDHC2_BASE_ADDR, 0, 8},
333#else
334 {USDHC2_BASE_ADDR, 0, 4},
335#endif
336};
337
338#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
339#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
340#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
341#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
342
343int board_mmc_getcd(struct mmc *mmc)
344{
345 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
346 int ret = 0;
347
348 switch (cfg->esdhc_base) {
349 case USDHC1_BASE_ADDR:
350 ret = !gpio_get_value(USDHC1_CD_GPIO);
351 break;
352 case USDHC2_BASE_ADDR:
353#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
354 ret = 1;
355#else
356 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
357 ARRAY_SIZE(usdhc2_cd_pads));
358 gpio_direction_input(USDHC2_CD_GPIO);
359
360 /*
361 * Since it is the DAT3 pin, this pin is pulled to
362 * low voltage if no card
363 */
364 ret = gpio_get_value(USDHC2_CD_GPIO);
365
366 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
367 ARRAY_SIZE(usdhc2_dat3_pads));
368#endif
369 break;
370 }
371
372 return ret;
373}
374
375int board_mmc_init(bd_t *bis)
376{
377#ifdef CONFIG_SPL_BUILD
378#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
379 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
380 ARRAY_SIZE(usdhc2_emmc_pads));
381#else
382 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
383#endif
384 gpio_direction_output(USDHC2_PWR_GPIO, 0);
385 udelay(500);
386 gpio_direction_output(USDHC2_PWR_GPIO, 1);
387 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
388 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
389#else
390 int i, ret;
391
392 /*
393 * According to the board_mmc_init() the following map is done:
394 * (U-boot device node) (Physical Port)
395 * mmc0 USDHC1
396 * mmc1 USDHC2
397 */
398 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
399 switch (i) {
400 case 0:
401 imx_iomux_v3_setup_multiple_pads(
402 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
403 gpio_direction_input(USDHC1_CD_GPIO);
404 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
405
406 gpio_direction_output(USDHC1_PWR_GPIO, 0);
407 udelay(500);
408 gpio_direction_output(USDHC1_PWR_GPIO, 1);
409 break;
410 case 1:
411#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
412 imx_iomux_v3_setup_multiple_pads(
413 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
414#else
415 imx_iomux_v3_setup_multiple_pads(
416 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
417#endif
418 gpio_direction_output(USDHC2_PWR_GPIO, 0);
419 udelay(500);
420 gpio_direction_output(USDHC2_PWR_GPIO, 1);
421 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
422 break;
423 default:
424 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
425 return -EINVAL;
426 }
427
428 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
429 if (ret) {
430 printf("Warning: failed to initialize mmc dev %d\n", i);
431 return ret;
432 }
433 }
434#endif
435 return 0;
436}
437#endif
438
439#ifdef CONFIG_USB_EHCI_MX6
440#define USB_OTHERREGS_OFFSET 0x800
441#define UCTRL_PWR_POL (1 << 9)
442
443static iomux_v3_cfg_t const usb_otg_pads[] = {
444 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
445};
446
447/* At default the 3v3 enables the MIC2026 for VBUS power */
448static void setup_usb(void)
449{
450 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
451 ARRAY_SIZE(usb_otg_pads));
452}
453
454int board_usb_phy_mode(int port)
455{
456 if (port == 1)
457 return USB_INIT_HOST;
458 else
459 return usb_phy_mode(port);
460}
461
462int board_ehci_hcd_init(int port)
463{
464 u32 *usbnc_usb_ctrl;
465
466 if (port > 1)
467 return -EINVAL;
468
469 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
470 port * 4);
471
472 /* Set Power polarity */
473 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
474
475 return 0;
476}
477#endif
478
0d4cdb56
PF		 479#ifdef CONFIG_FEC_MXC
480/*
481 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
482 * be used for ENET1 or ENET2, cannot be used for both.
483 */
484static iomux_v3_cfg_t const fec1_pads[] = {
485 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
486 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
487 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
488 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
489 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
490 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
491 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
492 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
493 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
494 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
495};
496
497static iomux_v3_cfg_t const fec2_pads[] = {
498 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
499 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
500
501 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
502 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
503 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
504 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
505
506 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
507 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
508 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
509 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
510};
511
512static void setup_iomux_fec(int fec_id)
513{
514 if (fec_id == 0)
515 imx_iomux_v3_setup_multiple_pads(fec1_pads,
516 ARRAY_SIZE(fec1_pads));
517 else
518 imx_iomux_v3_setup_multiple_pads(fec2_pads,
519 ARRAY_SIZE(fec2_pads));
520}
521
522int board_eth_init(bd_t *bis)
523{
524 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
525
526 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
527 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
528}
529
530static int setup_fec(int fec_id)
531{
532 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
533 int ret;
534
535 if (fec_id == 0) {
536 /*
537 * Use 50M anatop loopback REF_CLK1 for ENET1,
538 * clear gpr1[13], set gpr1[17].
539 */
540 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
541 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
542 } else {
543 /*
544 * Use 50M anatop loopback REF_CLK2 for ENET2,
545 * clear gpr1[14], set gpr1[18].
546 */
547 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
548 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
549 }
550
551 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
552 if (ret)
553 return ret;
554
555 enable_enet_clk(1);
556
557 return 0;
558}
559
560int board_phy_config(struct phy_device *phydev)
561{
562 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
563
564 if (phydev->drv->config)
565 phydev->drv->config(phydev);
566
567 return 0;
568}
569#endif
570
f0ff57b0
PF		 571int board_early_init_f(void)
572{
573 setup_iomux_uart();
574
575 return 0;
576}
577
578int board_init(void)
579{
580 /* Address of boot parameters */
581 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
582
583 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
584
585 iox74lv_init();
586
587#ifdef CONFIG_SYS_I2C_MXC
588 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
589#endif
590
0d4cdb56
PF		 591#ifdef CONFIG_FEC_MXC
592 setup_fec(CONFIG_FEC_ENET_DEV);
593#endif
594
f0ff57b0
PF		 595#ifdef CONFIG_USB_EHCI_MX6
596 setup_usb();
597#endif
598
599#ifdef CONFIG_FSL_QSPI
600 board_qspi_init();
601#endif
602
603 return 0;
604}
605
606#ifdef CONFIG_CMD_BMODE
607static const struct boot_mode board_boot_modes[] = {
608 /* 4 bit bus width */
609 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
610 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
611 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
612 {NULL, 0},
613};
614#endif
615
616int board_late_init(void)
617{
618#ifdef CONFIG_CMD_BMODE
619 add_board_boot_modes(board_boot_modes);
620#endif
621
d9cbb264
PF		 622#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
623 setenv("board_name", "EVK");
624
625 if (is_mx6ul_9x9_evk())
626 setenv("board_rev", "9X9");
627 else
628 setenv("board_rev", "14X14");
629#endif
630
f0ff57b0
PF		 631 return 0;
632}
633
634u32 get_board_rev(void)
635{
636 return get_cpu_rev();
637}
638
639int checkboard(void)
640{
d9cbb264
PF		 641 if (is_mx6ul_9x9_evk())
642 puts("Board: MX6UL 9x9 EVK\n");
643 else
644 puts("Board: MX6UL 14x14 EVK\n");
f0ff57b0
PF		 645
646 return 0;
647}
648
649#ifdef CONFIG_SPL_BUILD
650#include <libfdt.h>
651#include <spl.h>
652#include <asm/arch/mx6-ddr.h>
653
d9cbb264
PF		 654
655static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
656 .grp_addds = 0x00000030,
657 .grp_ddrmode_ctl = 0x00020000,
658 .grp_b0ds = 0x00000030,
659 .grp_ctlds = 0x00000030,
660 .grp_b1ds = 0x00000030,
661 .grp_ddrpke = 0x00000000,
662 .grp_ddrmode = 0x00020000,
663#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
664 .grp_ddr_type = 0x00080000,
665#else
666 .grp_ddr_type = 0x000c0000,
667#endif
668};
669
670#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
671static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
672 .dram_dqm0 = 0x00000030,
673 .dram_dqm1 = 0x00000030,
674 .dram_ras = 0x00000030,
675 .dram_cas = 0x00000030,
676 .dram_odt0 = 0x00000000,
677 .dram_odt1 = 0x00000000,
678 .dram_sdba2 = 0x00000000,
679 .dram_sdclk_0 = 0x00000030,
680 .dram_sdqs0 = 0x00003030,
681 .dram_sdqs1 = 0x00003030,
682 .dram_reset = 0x00000030,
683};
684
685static struct mx6_mmdc_calibration mx6_mmcd_calib = {
686 .p0_mpwldectrl0 = 0x00000000,
687 .p0_mpdgctrl0 = 0x20000000,
688 .p0_mprddlctl = 0x4040484f,
689 .p0_mpwrdlctl = 0x40405247,
690 .mpzqlp2ctl = 0x1b4700c7,
691};
692
693static struct mx6_lpddr2_cfg mem_ddr = {
694 .mem_speed = 800,
695 .density = 2,
696 .width = 16,
697 .banks = 4,
698 .rowaddr = 14,
699 .coladdr = 10,
700 .trcd_lp = 1500,
701 .trppb_lp = 1500,
702 .trpab_lp = 2000,
703 .trasmin = 4250,
704};
705
706struct mx6_ddr_sysinfo ddr_sysinfo = {
707 .dsize = 0,
708 .cs_density = 18,
709 .ncs = 1,
710 .cs1_mirror = 0,
711 .walat = 0,
712 .ralat = 5,
713 .mif3_mode = 3,
714 .bi_on = 1,
715 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
716 .rtt_nom = 0,
717 .sde_to_rst = 0, /* LPDDR2 does not need this field */
718 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
719 .ddr_type = DDR_TYPE_LPDDR2,
720};
721
722#else
723static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
f0ff57b0
PF		 724 .dram_dqm0 = 0x00000030,
725 .dram_dqm1 = 0x00000030,
726 .dram_ras = 0x00000030,
727 .dram_cas = 0x00000030,
728 .dram_odt0 = 0x00000030,
729 .dram_odt1 = 0x00000030,
730 .dram_sdba2 = 0x00000000,
731 .dram_sdclk_0 = 0x00000008,
732 .dram_sdqs0 = 0x00000038,
733 .dram_sdqs1 = 0x00000030,
734 .dram_reset = 0x00000030,
735};
736
d9cbb264 737static struct mx6_mmdc_calibration mx6_mmcd_calib = {
f0ff57b0
PF		 738 .p0_mpwldectrl0 = 0x00070007,
739 .p0_mpdgctrl0 = 0x41490145,
740 .p0_mprddlctl = 0x40404546,
741 .p0_mpwrdlctl = 0x4040524D,
742};
743
d9cbb264
PF		 744struct mx6_ddr_sysinfo ddr_sysinfo = {
745 .dsize = 0,
746 .cs_density = 20,
747 .ncs = 1,
748 .cs1_mirror = 0,
749 .rtt_wr = 2,
750 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
751 .walat = 1, /* Write additional latency */
752 .ralat = 5, /* Read additional latency */
753 .mif3_mode = 3, /* Command prediction working mode */
754 .bi_on = 1, /* Bank interleaving enabled */
755 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
756 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
757 .ddr_type = DDR_TYPE_DDR3,
758};
759
f0ff57b0
PF		 760static struct mx6_ddr3_cfg mem_ddr = {
761 .mem_speed = 800,
762 .density = 4,
763 .width = 16,
764 .banks = 8,
765 .rowaddr = 15,
766 .coladdr = 10,
767 .pagesz = 2,
768 .trcd = 1375,
769 .trcmin = 4875,
770 .trasmin = 3500,
771};
d9cbb264 772#endif
f0ff57b0
PF		 773
774static void ccgr_init(void)
775{
776 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
777
778 writel(0xFFFFFFFF, &ccm->CCGR0);
779 writel(0xFFFFFFFF, &ccm->CCGR1);
780 writel(0xFFFFFFFF, &ccm->CCGR2);
781 writel(0xFFFFFFFF, &ccm->CCGR3);
782 writel(0xFFFFFFFF, &ccm->CCGR4);
783 writel(0xFFFFFFFF, &ccm->CCGR5);
784 writel(0xFFFFFFFF, &ccm->CCGR6);
785 writel(0xFFFFFFFF, &ccm->CCGR7);
786}
787
788static void spl_dram_init(void)
789{
f0ff57b0 790 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
d9cbb264 791 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
f0ff57b0
PF		 792}
793
794void board_init_f(ulong dummy)
795{
796 /* setup AIPS and disable watchdog */
797 arch_cpu_init();
798
799 ccgr_init();
800
801 /* iomux and setup of i2c */
802 board_early_init_f();
803
804 /* setup GP timer */
805 timer_init();
806
807 /* UART clocks enabled and gd valid - init serial console */
808 preloader_console_init();
809
810 /* DDR initialization */
811 spl_dram_init();
812
813 /* Clear the BSS. */
814 memset(__bss_start, 0, __bss_end - __bss_start);
815
816 /* load/boot image from boot device */
817 board_init_r(NULL, 0);
818}
819
820void reset_cpu(ulong addr)
821{
822}
823#endif
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