[thirdparty/u-boot.git] / board / freescale / p1010rdb / p1010rdb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * Copyright 2020 NXP
 */

#include <common.h>
#include <command.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <pci.h>
#include <asm/fsl_serdes.h>
#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include <hwconfig.h>
#include <i2c.h>

DECLARE_GLOBAL_DATA_PTR;

#define GPIO4_PCIE_RESET_SET		0x08000000
#define MUX_CPLD_CAN_UART		0x00
#define MUX_CPLD_TDM			0x01
#define MUX_CPLD_SPICS0_FLASH		0x00
#define MUX_CPLD_SPICS0_SLIC		0x02
#define PMUXCR1_IFC_MASK       0x00ffff00
#define PMUXCR1_SDHC_MASK      0x00fff000
#define PMUXCR1_SDHC_ENABLE    0x00555000

enum {
	MUX_TYPE_IFC,
	MUX_TYPE_SDHC,
	MUX_TYPE_SPIFLASH,
	MUX_TYPE_TDM,
	MUX_TYPE_CAN,
	MUX_TYPE_CS0_NOR,
	MUX_TYPE_CS0_NAND,
};

enum {
	I2C_READ_BANK,
	I2C_READ_PCB_VER,
};

static uint sd_ifc_mux;

struct cpld_data {
	u8 cpld_ver; /* cpld revision */
#if defined(CONFIG_TARGET_P1010RDB_PA)
	u8 pcba_ver; /* pcb revision number */
	u8 twindie_ddr3;
	u8 res1[6];
	u8 bank_sel; /* NOR Flash bank */
	u8 res2[5];
	u8 usb2_sel;
	u8 res3[1];
	u8 porsw_sel;
	u8 tdm_can_sel;
	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
	u8 por0; /* POR Options */
	u8 por1; /* POR Options */
	u8 por2; /* POR Options */
	u8 por3; /* POR Options */
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	u8 rom_loc;
#endif
};

int board_early_init_f(void)
{
	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
	/* Clock configuration to access CPLD using IFC(GPCM) */
	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
	/*
	* Reset PCIe slots via GPIO4
	*/
	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);

	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_16M, 1);

	set_tlb(1, flashbase + 0x1000000,
			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
	return 0;
}

#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */

int config_board_mux(int ctrl_type)
{
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u8 tmp;

#ifdef CONFIG_DM_I2C
	struct udevice *dev;
	int ret;
#if defined(CONFIG_TARGET_P1010RDB_PA)
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);

	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
				      I2C_PCA9557_ADDR1, 1, &dev);
	if (ret) {
		printf("%s: Cannot find udev for a bus %d\n",
		       __func__, I2C_PCA9557_BUS_NUM);
		return ret;
	}
	switch (ctrl_type) {
	case MUX_TYPE_IFC:
		tmp = 0xf0;
		dm_i2c_write(dev, 3, &tmp, 1);
		tmp = 0x01;
		dm_i2c_write(dev, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_IFC;
		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
		break;
	case MUX_TYPE_SDHC:
		tmp = 0xf0;
		dm_i2c_write(dev, 3, &tmp, 1);
		tmp = 0x05;
		dm_i2c_write(dev, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_SDHC;
		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
				PMUXCR1_SDHC_ENABLE);
		break;
	case MUX_TYPE_SPIFLASH:
		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
		break;
	case MUX_TYPE_TDM:
		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
		break;
	case MUX_TYPE_CAN:
		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
		break;
	default:
		break;
	}
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
				      I2C_PCA9557_ADDR2, 1, &dev);
	if (ret) {
		printf("%s: Cannot find udev for a bus %d\n",
		       __func__, I2C_PCA9557_BUS_NUM);
		return ret;
	}
	switch (ctrl_type) {
	case MUX_TYPE_IFC:
		dm_i2c_read(dev, 0, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		dm_i2c_write(dev, 3, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_IFC;
		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
		break;
	case MUX_TYPE_SDHC:
		dm_i2c_read(dev, 0, &tmp, 1);
		setbits_8(&tmp, 0x04);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		dm_i2c_write(dev, 3, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_SDHC;
		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
				PMUXCR1_SDHC_ENABLE);
		break;
	case MUX_TYPE_SPIFLASH:
		dm_i2c_read(dev, 0, &tmp, 1);
		clrbits_8(&tmp, 0x80);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x80);
		dm_i2c_write(dev, 3, &tmp, 1);
		break;
	case MUX_TYPE_TDM:
		dm_i2c_read(dev, 0, &tmp, 1);
		setbits_8(&tmp, 0x82);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x82);
		dm_i2c_write(dev, 3, &tmp, 1);
		break;
	case MUX_TYPE_CAN:
		dm_i2c_read(dev, 0, &tmp, 1);
		clrbits_8(&tmp, 0x02);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x02);
		dm_i2c_write(dev, 3, &tmp, 1);
		break;
	case MUX_TYPE_CS0_NOR:
		dm_i2c_read(dev, 0, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		dm_i2c_write(dev, 3, &tmp, 1);
		break;
	case MUX_TYPE_CS0_NAND:
		dm_i2c_read(dev, 0, &tmp, 1);
		setbits_8(&tmp, 0x08);
		dm_i2c_write(dev, 1, &tmp, 1);
		dm_i2c_read(dev, 3, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		dm_i2c_write(dev, 3, &tmp, 1);
		break;
	default:
		break;
	}
#endif
#else
#if defined(CONFIG_TARGET_P1010RDB_PA)
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);

	switch (ctrl_type) {
	case MUX_TYPE_IFC:
		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
		tmp = 0xf0;
		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
		tmp = 0x01;
		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_IFC;
		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
		break;
	case MUX_TYPE_SDHC:
		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
		tmp = 0xf0;
		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
		tmp = 0x05;
		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_SDHC;
		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
				PMUXCR1_SDHC_ENABLE);
		break;
	case MUX_TYPE_SPIFLASH:
		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
		break;
	case MUX_TYPE_TDM:
		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
		break;
	case MUX_TYPE_CAN:
		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
		break;
	default:
		break;
	}
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	uint orig_bus = i2c_get_bus_num();
	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);

	switch (ctrl_type) {
	case MUX_TYPE_IFC:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_IFC;
		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
		break;
	case MUX_TYPE_SDHC:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		setbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x04);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		sd_ifc_mux = MUX_TYPE_SDHC;
		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
				PMUXCR1_SDHC_ENABLE);
		break;
	case MUX_TYPE_SPIFLASH:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x80);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x80);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_TDM:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		setbits_8(&tmp, 0x82);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x82);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_CAN:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x02);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x02);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_CS0_NOR:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	case MUX_TYPE_CS0_NAND:
		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
		setbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		clrbits_8(&tmp, 0x08);
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
		break;
	default:
		break;
	}
	i2c_set_bus_num(orig_bus);
#endif
#endif
	return 0;
}

#ifdef CONFIG_TARGET_P1010RDB_PB
int i2c_pca9557_read(int type)
{
	u8 val;
	int bus_num = I2C_PCA9557_BUS_NUM;

#ifdef CONFIG_DM_I2C
	struct udevice *dev;
	int ret;

	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
	if (ret) {
		printf("%s: Cannot find udev for a bus %d\n",
		       __func__, bus_num);
		return ret;
	}
	dm_i2c_read(dev, 0, &val, 1);
#else
	i2c_set_bus_num(bus_num);
	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
#endif

	switch (type) {
	case I2C_READ_BANK:
		val = (val & 0x10) >> 4;
		break;
	case I2C_READ_PCB_VER:
		val = ((val & 0x60) >> 5) + 1;
		break;
	default:
		break;
	}

	return val;
}
#endif

int checkboard(void)
{
	struct cpu_type *cpu;
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
	u8 val;

	cpu = gd->arch.cpu;
#if defined(CONFIG_TARGET_P1010RDB_PA)
	printf("Board: %sRDB-PA, ", cpu->name);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	printf("Board: %sRDB-PB, ", cpu->name);
#ifdef CONFIG_DM_I2C
	struct udevice *dev;
	int ret;

	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
				      1, &dev);
	if (ret) {
		printf("%s: Cannot find udev for a bus %d\n", __func__,
		       I2C_PCA9557_BUS_NUM);
		return ret;
	}
	val = 0x0;  /* no polarity inversion */
	dm_i2c_write(dev, 2, &val, 1);
#else
	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
	val = 0x0;  /* no polarity inversion */
	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
#endif
#endif

#ifdef CONFIG_SDCARD
	/* switch to IFC to read info from CPLD */
	config_board_mux(MUX_TYPE_IFC);
#endif

#if defined(CONFIG_TARGET_P1010RDB_PA)
	val = (in_8(&cpld_data->pcba_ver) & 0xf);
	printf("PCB: v%x.0\n", val);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
	val = in_8(&cpld_data->cpld_ver);
	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
	val = in_8(&cpld_data->rom_loc) & 0xf;
	puts("Boot from: ");
	switch (val) {
	case 0xf:
		config_board_mux(MUX_TYPE_CS0_NOR);
		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
		break;
	case 0xe:
		puts("SDHC\n");
		val = 0x60; /* set pca9557 pin input/output */
#ifdef CONFIG_DM_I2C
		dm_i2c_write(dev, 3, &val, 1);
#else
		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
#endif
		break;
	case 0x5:
		config_board_mux(MUX_TYPE_IFC);
		config_board_mux(MUX_TYPE_CS0_NAND);
		puts("NAND\n");
		break;
	case 0x6:
		config_board_mux(MUX_TYPE_IFC);
		puts("SPI\n");
		break;
	default:
		puts("unknown\n");
		break;
	}
#endif
	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	struct cpu_type *cpu;
	int num = 0;

	cpu = gd->arch.cpu;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif
#ifdef CONFIG_TSEC3
	/* P1014 and it's derivatives do not support eTSEC3 */
	if (cpu->soc_ver != SVR_P1014) {
		SET_STD_TSEC_INFO(tsec_info[num], 3);
		num++;
	}
#endif
	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;

	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);
#endif

	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"fsl,p1010-flexcan")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_spi_flash(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"spansion,s25sl12801")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_spi_slic(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"zarlink,le88266")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_tdm(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"fsl,starlite-tdm")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_sdhc(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
			"fsl,esdhc")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_del_ifc(void *blob)
{
	int nodeoff = 0;

	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
				"fsl,ifc")) >= 0) {
		fdt_del_node(blob, nodeoff);
	}
}

void fdt_disable_uart1(void *blob)
{
	int nodeoff;

	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
					CONFIG_SYS_NS16550_COM2);

	if (nodeoff > 0) {
		fdt_status_disabled(blob, nodeoff);
	} else {
		printf("WARNING unable to set status for fsl,ns16550 "
			"uart1: %s\n", fdt_strerror(nodeoff));
	}
}

int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;
	struct cpu_type *cpu;

	cpu = gd->arch.cpu;

	ft_cpu_setup(blob, bd);

	base = env_get_bootm_low();
	size = env_get_bootm_size();

#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
	FT_FSL_PCI_SETUP;
#endif

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#if defined(CONFIG_HAS_FSL_DR_USB)
	fsl_fdt_fixup_dr_usb(blob, bd);
#endif

       /* P1014 and it's derivatives don't support CAN and eTSEC3 */
	if (cpu->soc_ver == SVR_P1014) {
		fdt_del_flexcan(blob);
		fdt_del_node_and_alias(blob, "ethernet2");
	}

	/* Delete IFC node as IFC pins are multiplexing with SDHC */
	if (sd_ifc_mux != MUX_TYPE_IFC)
		fdt_del_ifc(blob);
	else
		fdt_del_sdhc(blob);

	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
		fdt_del_tdm(blob);
		fdt_del_spi_slic(blob);
	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
		fdt_del_flexcan(blob);
		fdt_del_spi_flash(blob);
		fdt_disable_uart1(blob);
	} else {
		/*
		 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
		 * explicitly, defaultly spi_cs_sel to spi-flash instead of
		 * to tdm/slic.
		 */
		fdt_del_tdm(blob);
		fdt_del_flexcan(blob);
		fdt_disable_uart1(blob);
	}

	return 0;
}
#endif

#ifdef CONFIG_SDCARD
int board_mmc_init(bd_t *bis)
{
	config_board_mux(MUX_TYPE_SDHC);
		return -1;
}
#else
void board_reset(void)
{
	/* mux to IFC to enable CPLD for reset */
	if (sd_ifc_mux != MUX_TYPE_IFC)
		config_board_mux(MUX_TYPE_IFC);
}
#endif


int misc_init_r(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
				MPC85xx_PMUXCR_CAN1_UART |
				MPC85xx_PMUXCR_CAN2_TDM |
				MPC85xx_PMUXCR_CAN2_UART);
		config_board_mux(MUX_TYPE_CAN);
	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
				MPC85xx_PMUXCR_CAN1_UART);
		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
				MPC85xx_PMUXCR_CAN1_TDM);
		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
		config_board_mux(MUX_TYPE_TDM);
	} else {
		/* defaultly spi_cs_sel to flash */
		config_board_mux(MUX_TYPE_SPIFLASH);
	}

	if (hwconfig("esdhc"))
		config_board_mux(MUX_TYPE_SDHC);
	else if (hwconfig("ifc"))
		config_board_mux(MUX_TYPE_IFC);

#ifdef CONFIG_TARGET_P1010RDB_PB
	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
#endif
	return 0;
}

#ifndef CONFIG_SPL_BUILD
static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
		       char *const argv[])
{
	if (argc < 2)
		return CMD_RET_USAGE;
	if (strcmp(argv[1], "ifc") == 0)
		config_board_mux(MUX_TYPE_IFC);
	else if (strcmp(argv[1], "sdhc") == 0)
		config_board_mux(MUX_TYPE_SDHC);
	else
		return CMD_RET_USAGE;
	return 0;
}

U_BOOT_CMD(
	mux, 2, 0, pin_mux_cmd,
	"configure multiplexing pin for IFC/SDHC bus in runtime",
	"bus_type (e.g. mux sdhc)"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
49249e13 PA	2	/*
49249e13 PA	3	* Copyright 2010-2011 Freescale Semiconductor, Inc.
2703e640	4	* Copyright 2020 NXP
49249e13 PA	5	*/
	6
	7	#include <common.h>
09140113	8	#include <command.h>
4d72caa5	9	#include <image.h>
5255932f	10	#include <init.h>
90526e9f	11	#include <net.h>
49249e13 PA	12	#include <asm/processor.h>
	13	#include <asm/mmu.h>
	14	#include <asm/cache.h>
	15	#include <asm/immap_85xx.h>
	16	#include <asm/io.h>
7b51b576	17	#include <env.h>
49249e13	18	#include <miiphy.h>
b08c8c48	19	#include <linux/libfdt.h>
49249e13 PA	20	#include <fdt_support.h>
	21	#include <fsl_mdio.h>
	22	#include <tsec.h>
	23	#include <mmc.h>
	24	#include <netdev.h>
	25	#include <pci.h>
	26	#include <asm/fsl_serdes.h>
0b66513b	27	#include <fsl_ifc.h>
49249e13	28	#include <asm/fsl_pci.h>
49249e13	29	#include <hwconfig.h>
ad89da0c	30	#include <i2c.h>
49249e13 PA	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	#define GPIO4_PCIE_RESET_SET 0x08000000
	35	#define MUX_CPLD_CAN_UART 0x00
	36	#define MUX_CPLD_TDM 0x01
	37	#define MUX_CPLD_SPICS0_FLASH 0x00
	38	#define MUX_CPLD_SPICS0_SLIC 0x02
ad89da0c SL	39	#define PMUXCR1_IFC_MASK 0x00ffff00
	40	#define PMUXCR1_SDHC_MASK 0x00fff000
	41	#define PMUXCR1_SDHC_ENABLE 0x00555000
	42
	43	enum {
	44	MUX_TYPE_IFC,
	45	MUX_TYPE_SDHC,
e512c50b SL	46	MUX_TYPE_SPIFLASH,
	47	MUX_TYPE_TDM,
	48	MUX_TYPE_CAN,
	49	MUX_TYPE_CS0_NOR,
	50	MUX_TYPE_CS0_NAND,
	51	};
	52
	53	enum {
	54	I2C_READ_BANK,
	55	I2C_READ_PCB_VER,
ad89da0c SL	56	};
	57
	58	static uint sd_ifc_mux;
49249e13	59
49249e13 PA	60	struct cpld_data {
49249e13 PA	61	u8 cpld_ver; /* cpld revision */
7601686c	62	#if defined(CONFIG_TARGET_P1010RDB_PA)
49249e13 PA	63	u8 pcba_ver; /* pcb revision number */
	64	u8 twindie_ddr3;
	65	u8 res1[6];
	66	u8 bank_sel; /* NOR Flash bank */
	67	u8 res2[5];
	68	u8 usb2_sel;
	69	u8 res3[1];
	70	u8 porsw_sel;
	71	u8 tdm_can_sel;
	72	u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
	73	u8 por0; /* POR Options */
	74	u8 por1; /* POR Options */
	75	u8 por2; /* POR Options */
	76	u8 por3; /* POR Options */
7601686c	77	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	78	u8 rom_loc;
e512c50b SL	79	#endif
49249e13	80	};
49249e13 PA	81
	82	int board_early_init_f(void)
	83	{
	84	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
39b0bbbb	85	struct fsl_ifc ifc = {(void )CONFIG_SYS_IFC_ADDR, (void )NULL};
49249e13	86	/* Clock configuration to access CPLD using IFC(GPCM) */
39b0bbbb	87	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
49249e13 PA	88	/*
	89	* Reset PCIe slots via GPIO4
	90	*/
	91	setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
	92	setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
	93
	94	return 0;
	95	}
	96
	97	int board_early_init_r(void)
	98	{
49249e13	99	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	100	int flash_esel = find_tlb_idx((void *)flashbase, 1);
49249e13 PA	101
	102	/*
	103	* Remap Boot flash region to caching-inhibited
	104	* so that flash can be erased properly.
	105	*/
	106
	107	/* Flush d-cache and invalidate i-cache of any FLASH data */
	108	flush_dcache();
	109	invalidate_icache();
	110
9d045682 YS	111	if (flash_esel == -1) {
	112	/* very unlikely unless something is messed up */
	113	puts("Error: Could not find TLB for FLASH BASE\n");
	114	flash_esel = 2; /* give our best effort to continue */
	115	} else {
	116	/* invalidate existing TLB entry for flash */
	117	disable_tlb(flash_esel);
	118	}
49249e13 PA	119
	120	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	121	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	122	0, flash_esel, BOOKE_PAGESZ_16M, 1);
	123
	124	set_tlb(1, flashbase + 0x1000000,
	125	CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
	126	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	127	0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
49249e13 PA	128	return 0;
	129	}
	130
177edd82	131	#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
49249e13 PA	132	void pci_init_board(void)
	133	{
	134	fsl_pcie_init_board(0);
	135	}
	136	#endif /* ifdef CONFIG_PCI */
	137
ad89da0c SL	138	int config_board_mux(int ctrl_type)
	139	{
	140	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	141	u8 tmp;
	142
2703e640 BL	143	#ifdef CONFIG_DM_I2C
	144	struct udevice *dev;
	145	int ret;
	146	#if defined(CONFIG_TARGET_P1010RDB_PA)
	147	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
	148
	149	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
	150	I2C_PCA9557_ADDR1, 1, &dev);
	151	if (ret) {
	152	printf("%s: Cannot find udev for a bus %d\n",
	153	__func__, I2C_PCA9557_BUS_NUM);
	154	return ret;
	155	}
	156	switch (ctrl_type) {
	157	case MUX_TYPE_IFC:
	158	tmp = 0xf0;
	159	dm_i2c_write(dev, 3, &tmp, 1);
	160	tmp = 0x01;
	161	dm_i2c_write(dev, 1, &tmp, 1);
	162	sd_ifc_mux = MUX_TYPE_IFC;
	163	clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
	164	break;
	165	case MUX_TYPE_SDHC:
	166	tmp = 0xf0;
	167	dm_i2c_write(dev, 3, &tmp, 1);
	168	tmp = 0x05;
	169	dm_i2c_write(dev, 1, &tmp, 1);
	170	sd_ifc_mux = MUX_TYPE_SDHC;
	171	clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
	172	PMUXCR1_SDHC_ENABLE);
	173	break;
	174	case MUX_TYPE_SPIFLASH:
	175	out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
	176	break;
	177	case MUX_TYPE_TDM:
	178	out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
	179	out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
	180	break;
	181	case MUX_TYPE_CAN:
	182	out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
	183	break;
	184	default:
	185	break;
	186	}
	187	#elif defined(CONFIG_TARGET_P1010RDB_PB)
	188	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
	189	I2C_PCA9557_ADDR2, 1, &dev);
	190	if (ret) {
	191	printf("%s: Cannot find udev for a bus %d\n",
	192	__func__, I2C_PCA9557_BUS_NUM);
	193	return ret;
	194	}
	195	switch (ctrl_type) {
	196	case MUX_TYPE_IFC:
	197	dm_i2c_read(dev, 0, &tmp, 1);
	198	clrbits_8(&tmp, 0x04);
	199	dm_i2c_write(dev, 1, &tmp, 1);
	200	dm_i2c_read(dev, 3, &tmp, 1);
	201	clrbits_8(&tmp, 0x04);
	202	dm_i2c_write(dev, 3, &tmp, 1);
	203	sd_ifc_mux = MUX_TYPE_IFC;
	204	clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
	205	break;
	206	case MUX_TYPE_SDHC:
207	dm_i2c_read(dev, 0, &tmp, 1);
208	setbits_8(&tmp, 0x04);
209	dm_i2c_write(dev, 1, &tmp, 1);
210	dm_i2c_read(dev, 3, &tmp, 1);
211	clrbits_8(&tmp, 0x04);
212	dm_i2c_write(dev, 3, &tmp, 1);
213	sd_ifc_mux = MUX_TYPE_SDHC;
214	clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
215	PMUXCR1_SDHC_ENABLE);
216	break;
217	case MUX_TYPE_SPIFLASH:
218	dm_i2c_read(dev, 0, &tmp, 1);
219	clrbits_8(&tmp, 0x80);
220	dm_i2c_write(dev, 1, &tmp, 1);
221	dm_i2c_read(dev, 3, &tmp, 1);
222	clrbits_8(&tmp, 0x80);
223	dm_i2c_write(dev, 3, &tmp, 1);
224	break;
225	case MUX_TYPE_TDM:
226	dm_i2c_read(dev, 0, &tmp, 1);
227	setbits_8(&tmp, 0x82);
228	dm_i2c_write(dev, 1, &tmp, 1);
229	dm_i2c_read(dev, 3, &tmp, 1);
230	clrbits_8(&tmp, 0x82);
231	dm_i2c_write(dev, 3, &tmp, 1);
232	break;
233	case MUX_TYPE_CAN:
234	dm_i2c_read(dev, 0, &tmp, 1);
235	clrbits_8(&tmp, 0x02);
236	dm_i2c_write(dev, 1, &tmp, 1);
237	dm_i2c_read(dev, 3, &tmp, 1);
238	clrbits_8(&tmp, 0x02);
239	dm_i2c_write(dev, 3, &tmp, 1);
240	break;
241	case MUX_TYPE_CS0_NOR:
242	dm_i2c_read(dev, 0, &tmp, 1);
243	clrbits_8(&tmp, 0x08);
244	dm_i2c_write(dev, 1, &tmp, 1);
245	dm_i2c_read(dev, 3, &tmp, 1);
246	clrbits_8(&tmp, 0x08);
247	dm_i2c_write(dev, 3, &tmp, 1);
248	break;
249	case MUX_TYPE_CS0_NAND:
250	dm_i2c_read(dev, 0, &tmp, 1);
251	setbits_8(&tmp, 0x08);
252	dm_i2c_write(dev, 1, &tmp, 1);
253	dm_i2c_read(dev, 3, &tmp, 1);
254	clrbits_8(&tmp, 0x08);
255	dm_i2c_write(dev, 3, &tmp, 1);
256	break;
257	default:
258	break;
259	}
260	#endif
261	#else
7601686c	262	#if defined(CONFIG_TARGET_P1010RDB_PA)
e512c50b SL	263	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
e512c50b SL	264
ad89da0c SL	265	switch (ctrl_type) {
	266	case MUX_TYPE_IFC:
	267	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	268	tmp = 0xf0;
	269	i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
	270	tmp = 0x01;
	271	i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
	272	sd_ifc_mux = MUX_TYPE_IFC;
	273	clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
	274	break;
	275	case MUX_TYPE_SDHC:
	276	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	277	tmp = 0xf0;
	278	i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
	279	tmp = 0x05;
	280	i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
	281	sd_ifc_mux = MUX_TYPE_SDHC;
	282	clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
	283	PMUXCR1_SDHC_ENABLE);
	284	break;
e512c50b SL	285	case MUX_TYPE_SPIFLASH:
	286	out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
	287	break;
	288	case MUX_TYPE_TDM:
	289	out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
	290	out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
	291	break;
	292	case MUX_TYPE_CAN:
	293	out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
	294	break;
ad89da0c SL	295	default:
	296	break;
	297	}
7601686c	298	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	299	uint orig_bus = i2c_get_bus_num();
e512c50b SL	300	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
ad89da0c	301
e512c50b SL	302	switch (ctrl_type) {
	303	case MUX_TYPE_IFC:
	304	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	305	clrbits_8(&tmp, 0x04);
	306	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	307	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	308	clrbits_8(&tmp, 0x04);
	309	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	310	sd_ifc_mux = MUX_TYPE_IFC;
	311	clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
	312	break;
	313	case MUX_TYPE_SDHC:
	314	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	315	setbits_8(&tmp, 0x04);
	316	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	317	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	318	clrbits_8(&tmp, 0x04);
	319	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	320	sd_ifc_mux = MUX_TYPE_SDHC;
	321	clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
	322	PMUXCR1_SDHC_ENABLE);
	323	break;
	324	case MUX_TYPE_SPIFLASH:
	325	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	326	clrbits_8(&tmp, 0x80);
	327	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	328	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	329	clrbits_8(&tmp, 0x80);
	330	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	331	break;
	332	case MUX_TYPE_TDM:
	333	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	334	setbits_8(&tmp, 0x82);
	335	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	336	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	337	clrbits_8(&tmp, 0x82);
	338	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	339	break;
	340	case MUX_TYPE_CAN:
	341	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	342	clrbits_8(&tmp, 0x02);
	343	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	344	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	345	clrbits_8(&tmp, 0x02);
	346	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	347	break;
	348	case MUX_TYPE_CS0_NOR:
	349	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	350	clrbits_8(&tmp, 0x08);
	351	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	352	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	353	clrbits_8(&tmp, 0x08);
	354	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	355	break;
	356	case MUX_TYPE_CS0_NAND:
	357	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
	358	setbits_8(&tmp, 0x08);
	359	i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
	360	i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	361	clrbits_8(&tmp, 0x08);
	362	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
	363	break;
	364	default:
	365	break;
366	}
367	i2c_set_bus_num(orig_bus);
2703e640	368	#endif
e512c50b	369	#endif
ad89da0c SL	370	return 0;
	371	}
	372
7601686c	373	#ifdef CONFIG_TARGET_P1010RDB_PB
e512c50b SL	374	int i2c_pca9557_read(int type)
	375	{
	376	u8 val;
2703e640	377	int bus_num = I2C_PCA9557_BUS_NUM;
e512c50b	378
2703e640 BL	379	#ifdef CONFIG_DM_I2C
	380	struct udevice *dev;
	381	int ret;
	382
	383	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
	384	if (ret) {
	385	printf("%s: Cannot find udev for a bus %d\n",
	386	__func__, bus_num);
	387	return ret;
	388	}
	389	dm_i2c_read(dev, 0, &val, 1);
	390	#else
	391	i2c_set_bus_num(bus_num);
e512c50b	392	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
2703e640	393	#endif
e512c50b SL	394
	395	switch (type) {
	396	case I2C_READ_BANK:
	397	val = (val & 0x10) >> 4;
	398	break;
	399	case I2C_READ_PCB_VER:
	400	val = ((val & 0x60) >> 5) + 1;
	401	break;
	402	default:
	403	break;
	404	}
	405
	406	return val;
	407	}
	408	#endif
	409
49249e13 PA	410	int checkboard(void)
	411	{
	412	struct cpu_type *cpu;
e512c50b SL	413	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
e512c50b SL	414	u8 val;
49249e13	415
67ac13b1	416	cpu = gd->arch.cpu;
7601686c	417	#if defined(CONFIG_TARGET_P1010RDB_PA)
e512c50b	418	printf("Board: %sRDB-PA, ", cpu->name);
7601686c	419	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b	420	printf("Board: %sRDB-PB, ", cpu->name);
2703e640 BL	421	#ifdef CONFIG_DM_I2C
	422	struct udevice *dev;
	423	int ret;
	424
	425	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
	426	1, &dev);
	427	if (ret) {
	428	printf("%s: Cannot find udev for a bus %d\n", __func__,
	429	I2C_PCA9557_BUS_NUM);
	430	return ret;
	431	}
	432	val = 0x0; /* no polarity inversion */
	433	dm_i2c_write(dev, 2, &val, 1);
	434	#else
e512c50b SL	435	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
	436	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
	437	val = 0x0; /* no polarity inversion */
	438	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
	439	#endif
2703e640	440	#endif
49249e13	441
ad89da0c SL	442	#ifdef CONFIG_SDCARD
	443	/* switch to IFC to read info from CPLD */
	444	config_board_mux(MUX_TYPE_IFC);
	445	#endif
	446
7601686c	447	#if defined(CONFIG_TARGET_P1010RDB_PA)
e512c50b SL	448	val = (in_8(&cpld_data->pcba_ver) & 0xf);
e512c50b SL	449	printf("PCB: v%x.0\n", val);
7601686c	450	#elif defined(CONFIG_TARGET_P1010RDB_PB)
e512c50b SL	451	val = in_8(&cpld_data->cpld_ver);
	452	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
	453	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
	454	val = in_8(&cpld_data->rom_loc) & 0xf;
	455	puts("Boot from: ");
	456	switch (val) {
	457	case 0xf:
	458	config_board_mux(MUX_TYPE_CS0_NOR);
	459	printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
	460	break;
	461	case 0xe:
	462	puts("SDHC\n");
	463	val = 0x60; /* set pca9557 pin input/output */
2703e640 BL	464	#ifdef CONFIG_DM_I2C
	465	dm_i2c_write(dev, 3, &val, 1);
	466	#else
e512c50b	467	i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
2703e640	468	#endif
e512c50b SL	469	break;
	470	case 0x5:
	471	config_board_mux(MUX_TYPE_IFC);
	472	config_board_mux(MUX_TYPE_CS0_NAND);
	473	puts("NAND\n");
	474	break;
	475	case 0x6:
	476	config_board_mux(MUX_TYPE_IFC);
	477	puts("SPI\n");
	478	break;
	479	default:
	480	puts("unknown\n");
	481	break;
	482	}
	483	#endif
49249e13 PA	484	return 0;
	485	}
	486
49249e13 PA	487	int board_eth_init(bd_t *bis)
49249e13 PA	488	{
c712df1d	489	#ifdef CONFIG_TSEC_ENET
49249e13 PA	490	struct fsl_pq_mdio_info mdio_info;
	491	struct tsec_info_struct tsec_info[4];
	492	struct cpu_type *cpu;
	493	int num = 0;
	494
67ac13b1	495	cpu = gd->arch.cpu;
49249e13 PA	496
	497	#ifdef CONFIG_TSEC1
	498	SET_STD_TSEC_INFO(tsec_info[num], 1);
	499	num++;
	500	#endif
	501	#ifdef CONFIG_TSEC2
	502	SET_STD_TSEC_INFO(tsec_info[num], 2);
	503	num++;
	504	#endif
	505	#ifdef CONFIG_TSEC3
	506	/* P1014 and it's derivatives do not support eTSEC3 */
48f6a5c3	507	if (cpu->soc_ver != SVR_P1014) {
49249e13 PA	508	SET_STD_TSEC_INFO(tsec_info[num], 3);
	509	num++;
	510	}
	511	#endif
	512	if (!num) {
	513	printf("No TSECs initialized\n");
	514	return 0;
	515	}
	516
	517	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	518	mdio_info.name = DEFAULT_MII_NAME;
	519
	520	fsl_pq_mdio_init(bis, &mdio_info);
	521
	522	tsec_eth_init(bis, tsec_info, num);
c712df1d	523	#endif
49249e13 PA	524
	525	return pci_eth_init(bis);
	526	}
49249e13 PA	527
	528	#if defined(CONFIG_OF_BOARD_SETUP)
	529	void fdt_del_flexcan(void *blob)
	530	{
	531	int nodeoff = 0;
	532
	533	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
f68a7305	534	"fsl,p1010-flexcan")) >= 0) {
49249e13 PA	535	fdt_del_node(blob, nodeoff);
	536	}
	537	}
	538
	539	void fdt_del_spi_flash(void *blob)
	540	{
	541	int nodeoff = 0;
	542
	543	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	544	"spansion,s25sl12801")) >= 0) {
	545	fdt_del_node(blob, nodeoff);
	546	}
	547	}
	548
	549	void fdt_del_spi_slic(void *blob)
	550	{
	551	int nodeoff = 0;
	552
	553	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	554	"zarlink,le88266")) >= 0) {
	555	fdt_del_node(blob, nodeoff);
	556	}
	557	}
	558
	559	void fdt_del_tdm(void *blob)
	560	{
	561	int nodeoff = 0;
	562
	563	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	564	"fsl,starlite-tdm")) >= 0) {
	565	fdt_del_node(blob, nodeoff);
	566	}
	567	}
	568
487e8abb SL	569	void fdt_del_sdhc(void *blob)
	570	{
	571	int nodeoff = 0;
	572
	573	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	574	"fsl,esdhc")) >= 0) {
	575	fdt_del_node(blob, nodeoff);
	576	}
	577	}
	578
ad89da0c SL	579	void fdt_del_ifc(void *blob)
	580	{
	581	int nodeoff = 0;
	582
	583	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	584	"fsl,ifc")) >= 0) {
	585	fdt_del_node(blob, nodeoff);
	586	}
	587	}
	588
487e8abb SL	589	void fdt_disable_uart1(void *blob)
	590	{
	591	int nodeoff;
	592
	593	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
	594	CONFIG_SYS_NS16550_COM2);
	595
	596	if (nodeoff > 0) {
	597	fdt_status_disabled(blob, nodeoff);
	598	} else {
	599	printf("WARNING unable to set status for fsl,ns16550 "
	600	"uart1: %s\n", fdt_strerror(nodeoff));
	601	}
	602	}
	603
e895a4b0	604	int ft_board_setup(void blob, bd_t bd)
49249e13 PA	605	{
	606	phys_addr_t base;
	607	phys_size_t size;
	608	struct cpu_type *cpu;
	609
67ac13b1	610	cpu = gd->arch.cpu;
49249e13 PA	611
	612	ft_cpu_setup(blob, bd);
	613
723806cc SG	614	base = env_get_bootm_low();
723806cc SG	615	size = env_get_bootm_size();
49249e13	616
177edd82	617	#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
49249e13 PA	618	FT_FSL_PCI_SETUP;
	619	#endif
	620
	621	fdt_fixup_memory(blob, (u64)base, (u64)size);
	622
a311db69	623	#if defined(CONFIG_HAS_FSL_DR_USB)
a5c289b9	624	fsl_fdt_fixup_dr_usb(blob, bd);
a311db69	625	#endif
49249e13 PA	626
49249e13 PA	627	/* P1014 and it's derivatives don't support CAN and eTSEC3 */
48f6a5c3	628	if (cpu->soc_ver == SVR_P1014) {
49249e13 PA	629	fdt_del_flexcan(blob);
	630	fdt_del_node_and_alias(blob, "ethernet2");
	631	}
ad89da0c SL	632
	633	/* Delete IFC node as IFC pins are multiplexing with SDHC */
	634	if (sd_ifc_mux != MUX_TYPE_IFC)
	635	fdt_del_ifc(blob);
	636	else
	637	fdt_del_sdhc(blob);
	638
49249e13	639	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
49249e13 PA	640	fdt_del_tdm(blob);
49249e13 PA	641	fdt_del_spi_slic(blob);
487e8abb	642	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
49249e13 PA	643	fdt_del_flexcan(blob);
49249e13 PA	644	fdt_del_spi_flash(blob);
487e8abb SL	645	fdt_disable_uart1(blob);
	646	} else {
	647	/*
	648	* If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
	649	* explicitly, defaultly spi_cs_sel to spi-flash instead of
	650	* to tdm/slic.
	651	*/
	652	fdt_del_tdm(blob);
	653	fdt_del_flexcan(blob);
	654	fdt_disable_uart1(blob);
49249e13	655	}
e895a4b0 SG	656
e895a4b0 SG	657	return 0;
ad89da0c	658	}
49249e13	659	#endif
ad89da0c SL	660
	661	#ifdef CONFIG_SDCARD
	662	int board_mmc_init(bd_t *bis)
	663	{
	664	config_board_mux(MUX_TYPE_SDHC);
	665	return -1;
	666	}
	667	#else
	668	void board_reset(void)
	669	{
	670	/* mux to IFC to enable CPLD for reset */
	671	if (sd_ifc_mux != MUX_TYPE_IFC)
	672	config_board_mux(MUX_TYPE_IFC);
49249e13 PA	673	}
	674	#endif
	675
ad89da0c	676
49249e13 PA	677	int misc_init_r(void)
49249e13 PA	678	{
49249e13 PA	679	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	680
	681	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
	682	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM \|
	683	MPC85xx_PMUXCR_CAN1_UART \|
	684	MPC85xx_PMUXCR_CAN2_TDM \|
	685	MPC85xx_PMUXCR_CAN2_UART);
e512c50b	686	config_board_mux(MUX_TYPE_CAN);
487e8abb	687	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
49249e13 PA	688	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART \|
	689	MPC85xx_PMUXCR_CAN1_UART);
	690	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM \|
	691	MPC85xx_PMUXCR_CAN1_TDM);
	692	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
	693	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
e512c50b	694	config_board_mux(MUX_TYPE_TDM);
487e8abb SL	695	} else {
487e8abb SL	696	/* defaultly spi_cs_sel to flash */
e512c50b	697	config_board_mux(MUX_TYPE_SPIFLASH);
487e8abb SL	698	}
487e8abb SL	699
ad89da0c SL	700	if (hwconfig("esdhc"))
	701	config_board_mux(MUX_TYPE_SDHC);
	702	else if (hwconfig("ifc"))
	703	config_board_mux(MUX_TYPE_IFC);
	704
7601686c	705	#ifdef CONFIG_TARGET_P1010RDB_PB
e512c50b SL	706	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
e512c50b SL	707	#endif
49249e13 PA	708	return 0;
49249e13 PA	709	}
ad89da0c	710
3a72a0ef	711	#ifndef CONFIG_SPL_BUILD
09140113 SG	712	static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	713	char *const argv[])
ad89da0c SL	714	{
	715	if (argc < 2)
	716	return CMD_RET_USAGE;
	717	if (strcmp(argv[1], "ifc") == 0)
	718	config_board_mux(MUX_TYPE_IFC);
	719	else if (strcmp(argv[1], "sdhc") == 0)
	720	config_board_mux(MUX_TYPE_SDHC);
	721	else
	722	return CMD_RET_USAGE;
	723	return 0;
	724	}
	725
	726	U_BOOT_CMD(
	727	mux, 2, 0, pin_mux_cmd,
	728	"configure multiplexing pin for IFC/SDHC bus in runtime",
	729	"bus_type (e.g. mux sdhc)"
	730	);
3a72a0ef	731	#endif