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7c8eea59 YZ |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
bf902566 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
7c8eea59 YZ |
5 | */ |
6 | ||
7 | #include <common.h> | |
24b852a7 | 8 | #include <console.h> |
203e94f6 | 9 | #include <environment.h> |
7c8eea59 YZ |
10 | #include <ns16550.h> |
11 | #include <malloc.h> | |
12 | #include <mmc.h> | |
13 | #include <nand.h> | |
14 | #include <i2c.h> | |
15 | #include "../common/ngpixis.h" | |
16 | #include <fsl_esdhc.h> | |
382ce7e9 | 17 | #include <spi_flash.h> |
ea022a37 | 18 | #include "../common/spl.h" |
7c8eea59 YZ |
19 | |
20 | DECLARE_GLOBAL_DATA_PTR; | |
21 | ||
22 | static const u32 sysclk_tbl[] = { | |
23 | 66666000, 7499900, 83332500, 8999900, | |
24 | 99999000, 11111000, 12499800, 13333200 | |
25 | }; | |
26 | ||
e3866163 | 27 | phys_size_t get_effective_memsize(void) |
7c8eea59 YZ |
28 | { |
29 | return CONFIG_SYS_L2_SIZE; | |
30 | } | |
31 | ||
32 | void board_init_f(ulong bootflag) | |
33 | { | |
34 | int px_spd; | |
35 | u32 plat_ratio, sys_clk, bus_clk; | |
36 | ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; | |
37 | ||
38 | console_init_f(); | |
39 | ||
40 | /* Set pmuxcr to allow both i2c1 and i2c2 */ | |
41 | setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); | |
42 | setbits_be32(&gur->pmuxcr, | |
43 | in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); | |
44 | ||
382ce7e9 YZ |
45 | #ifdef CONFIG_SPL_SPI_BOOT |
46 | /* Enable the SPI */ | |
47 | clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); | |
48 | #endif | |
49 | ||
7c8eea59 YZ |
50 | /* Read back the register to synchronize the write. */ |
51 | in_be32(&gur->pmuxcr); | |
52 | ||
53 | /* initialize selected port with appropriate baud rate */ | |
54 | px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); | |
55 | sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; | |
56 | plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; | |
57 | bus_clk = sys_clk * plat_ratio / 2; | |
58 | ||
59 | NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, | |
60 | bus_clk / 16 / CONFIG_BAUDRATE); | |
61 | #ifdef CONFIG_SPL_MMC_BOOT | |
62 | puts("\nSD boot...\n"); | |
382ce7e9 YZ |
63 | #elif defined(CONFIG_SPL_SPI_BOOT) |
64 | puts("\nSPI Flash boot...\n"); | |
7c8eea59 YZ |
65 | #endif |
66 | ||
67 | /* copy code to RAM and jump to it - this should not return */ | |
68 | /* NOTE - code has to be copied out of NAND buffer before | |
69 | * other blocks can be read. | |
70 | */ | |
71 | relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); | |
72 | } | |
73 | ||
74 | void board_init_r(gd_t *gd, ulong dest_addr) | |
75 | { | |
76 | /* Pointer is writable since we allocated a register for it */ | |
77 | gd = (gd_t *)CONFIG_SPL_GD_ADDR; | |
78 | bd_t *bd; | |
79 | ||
80 | memset(gd, 0, sizeof(gd_t)); | |
81 | bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); | |
82 | memset(bd, 0, sizeof(bd_t)); | |
83 | gd->bd = bd; | |
84 | bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; | |
85 | bd->bi_memsize = CONFIG_SYS_L2_SIZE; | |
86 | ||
cbcbf71b | 87 | arch_cpu_init(); |
7c8eea59 YZ |
88 | get_clocks(); |
89 | mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, | |
90 | CONFIG_SPL_RELOC_MALLOC_SIZE); | |
ed4708aa | 91 | gd->flags |= GD_FLG_FULL_MALLOC_INIT; |
5d97fe2a | 92 | #ifndef CONFIG_SPL_NAND_BOOT |
7c8eea59 | 93 | env_init(); |
5d97fe2a | 94 | #endif |
7c8eea59 YZ |
95 | #ifdef CONFIG_SPL_MMC_BOOT |
96 | mmc_initialize(bd); | |
97 | #endif | |
98 | /* relocate environment function pointers etc. */ | |
5d97fe2a YZ |
99 | #ifdef CONFIG_SPL_NAND_BOOT |
100 | nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, | |
101 | (uchar *)CONFIG_ENV_ADDR); | |
102 | ||
103 | gd->env_addr = (ulong)(CONFIG_ENV_ADDR); | |
203e94f6 | 104 | gd->env_valid = ENV_VALID; |
5d97fe2a | 105 | #else |
7c8eea59 | 106 | env_relocate(); |
5d97fe2a | 107 | #endif |
7c8eea59 | 108 | |
81b867aa YZ |
109 | #ifdef CONFIG_SYS_I2C |
110 | i2c_init_all(); | |
111 | #else | |
112 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
113 | #endif | |
7c8eea59 | 114 | |
f1683aa7 | 115 | dram_init(); |
5d97fe2a YZ |
116 | #ifdef CONFIG_SPL_NAND_BOOT |
117 | puts("Tertiary program loader running in sram..."); | |
118 | #else | |
7c8eea59 | 119 | puts("Second program loader running in sram...\n"); |
5d97fe2a | 120 | #endif |
7c8eea59 YZ |
121 | |
122 | #ifdef CONFIG_SPL_MMC_BOOT | |
123 | mmc_boot(); | |
382ce7e9 | 124 | #elif defined(CONFIG_SPL_SPI_BOOT) |
ea022a37 | 125 | fsl_spi_boot(); |
5d97fe2a YZ |
126 | #elif defined(CONFIG_SPL_NAND_BOOT) |
127 | nand_boot(); | |
7c8eea59 YZ |
128 | #endif |
129 | } |