[people/ms/u-boot.git] / board / freescale / p1022ds / tlb.c

/*
 * Copyright 2010 Freescale Semiconductor, Inc.
 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
 *          Timur Tabi <timur@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 */
	/* *I*** - Covers boot page */
	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
		      0, 0, BOOKE_PAGESZ_4K, 1),

	/* *I*G* - CCSRBAR */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_1M, 1),

#ifndef CONFIG_SPL_BUILD
	/* W**G* - Flash/promjet, localbus */
	/* This will be changed to *I*G* after relocation to RAM. */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
		      0, 2, BOOKE_PAGESZ_256M, 1),

	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_1G, 1),

	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 4, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_256M, 1),

	/* *I*G* - PCI I/O */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 6, BOOKE_PAGESZ_256K, 1),
#endif

	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 7, BOOKE_PAGESZ_4K, 1),

#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
	/* **** - eSDHC/eSPI/NAND boot */
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, 8, BOOKE_PAGESZ_1G, 1),
	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, 9, BOOKE_PAGESZ_1G, 1),
#endif

#ifdef CONFIG_SYS_NAND_BASE
	/* *I*G - NAND */
	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 10, BOOKE_PAGESZ_16K, 1),
#endif

};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
c59e1b4d TT	1	/*
	2	* Copyright 2010 Freescale Semiconductor, Inc.
	3	* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
	4	* Timur Tabi <timur@freescale.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the Free
	8	* Software Foundation; either version 2 of the License, or (at your option)
	9	* any later version.
	10	*/
	11
	12	#include <common.h>
	13	#include <asm/mmu.h>
	14
	15	struct fsl_e_tlb_entry tlb_table[] = {
	16	/* TLB 0 - for temp stack in cache */
	17	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
	18	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	19	0, 0, BOOKE_PAGESZ_4K, 0),
	20	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
	21	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
	22	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	23	0, 0, BOOKE_PAGESZ_4K, 0),
	24	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
	25	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
	26	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	27	0, 0, BOOKE_PAGESZ_4K, 0),
	28	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
	29	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
	30	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	31	0, 0, BOOKE_PAGESZ_4K, 0),
	32
	33	/* TLB 1 */
	34	/* I** - Covers boot page */
	35	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
	36	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I,
	37	0, 0, BOOKE_PAGESZ_4K, 1),
	38
	39	/* IG* - CCSRBAR */
	40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
	41	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	42	0, 1, BOOKE_PAGESZ_1M, 1),
	43
f45210d6	44	#ifndef CONFIG_SPL_BUILD
c59e1b4d TT	45	/* W*G - Flash/promjet, localbus */
	46	/* This will be changed to IG* after relocation to RAM. */
	47	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
	48	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
	49	0, 2, BOOKE_PAGESZ_256M, 1),
	50
	51	/* IG* - PCI */
	52	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
	53	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	54	0, 3, BOOKE_PAGESZ_1G, 1),
	55
	56	/* IG* - PCI */
	57	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
	58	CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
	59	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	60	0, 4, BOOKE_PAGESZ_256M, 1),
	61
	62	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
	63	CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
	64	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	65	0, 5, BOOKE_PAGESZ_256M, 1),
	66
	67	/* IG* - PCI I/O */
	68	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
	69	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	70	0, 6, BOOKE_PAGESZ_256K, 1),
f45210d6	71	#endif
c59e1b4d TT	72
	73	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
	74	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	75	0, 7, BOOKE_PAGESZ_4K, 1),
af253608	76
f45210d6 MM	77	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)
f45210d6 MM	78	/* **** - eSDHC/eSPI/NAND boot */
af253608 MM	79	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
	80	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	81	0, 8, BOOKE_PAGESZ_1G, 1),
f45210d6	82	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
af253608 MM	83	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
af253608 MM	84	CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
f45210d6	85	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
af253608 MM	86	0, 9, BOOKE_PAGESZ_1G, 1),
af253608 MM	87	#endif
f45210d6 MM	88
	89	#ifdef CONFIG_SYS_NAND_BASE
	90	/* IG - NAND */
	91	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
	92	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	93	0, 10, BOOKE_PAGESZ_16K, 1),
	94	#endif
	95
c59e1b4d TT	96	};
	97
	98	int num_tlb_entries = ARRAY_SIZE(tlb_table);