[people/ms/u-boot.git] / board / freescale / p1_p2_rdb / p1_p2_rdb.c

/*
 * Copyright 2009-2010 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <vsc7385.h>
#include <netdev.h>
#include <rtc.h>

DECLARE_GLOBAL_DATA_PTR;

#define VSC7385_RST_SET		0x00080000
#define SLIC_RST_SET		0x00040000
#define SGMII_PHY_RST_SET	0x00020000
#define PCIE_RST_SET		0x00010000
#define RGMII_PHY_RST_SET	0x02000000

#define USB_RST_CLR		0x04000000

#define GPIO_DIR		0x060f0000

#define BOARD_PERI_RST_SET	VSC7385_RST_SET | SLIC_RST_SET | \
				SGMII_PHY_RST_SET | PCIE_RST_SET | \
				RGMII_PHY_RST_SET

#define SYSCLK_MASK	0x00200000
#define BOARDREV_MASK	0x10100000
#define BOARDREV_B	0x10100000
#define BOARDREV_C	0x00100000
#define BOARDREV_D	0x00000000

#define SYSCLK_66	66666666
#define SYSCLK_50	50000000
#define SYSCLK_100	100000000

unsigned long get_board_sys_clk(ulong dummy)
{
	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val_gpdat, sysclk_gpio, board_rev_gpio;

	val_gpdat = in_be32(&pgpio->gpdat);
	sysclk_gpio = val_gpdat & SYSCLK_MASK;
	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	if (board_rev_gpio == BOARDREV_C) {
		if(sysclk_gpio == 0)
			return SYSCLK_66;
		else
			return SYSCLK_100;
	} else if (board_rev_gpio == BOARDREV_B) {
		if(sysclk_gpio == 0)
			return SYSCLK_66;
		else
			return SYSCLK_50;
	} else if (board_rev_gpio == BOARDREV_D) {
		if(sysclk_gpio == 0)
			return SYSCLK_66;
		else
			return SYSCLK_100;
	}
	return 0;
}

#ifdef CONFIG_MMC
int board_early_init_f (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->pmuxcr,
			(MPC85xx_PMUXCR_SDHC_CD |
			 MPC85xx_PMUXCR_SDHC_WP));
	return 0;
}
#endif

int checkboard (void)
{
	u32 val_gpdat, board_rev_gpio;
	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	char board_rev = 0;
	struct cpu_type *cpu;

	val_gpdat = in_be32(&pgpio->gpdat);
	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	if (board_rev_gpio == BOARDREV_C)
		board_rev = 'C';
	else if (board_rev_gpio == BOARDREV_B)
		board_rev = 'B';
	else if (board_rev_gpio == BOARDREV_D)
		board_rev = 'D';
	else
		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);

	cpu = gd->cpu;
	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
	setbits_be32(&pgpio->gpdir, GPIO_DIR);

/*
 * Bringing the following peripherals out of reset via GPIOs
 * 0 = reset and 1 = out of reset
 * GPIO12 - Reset to Ethernet Switch
 * GPIO13 - Reset to SLIC/SLAC devices
 * GPIO14 - Reset to SGMII_PHY_N
 * GPIO15 - Reset to PCIe slots
 * GPIO6  - Reset to RGMII PHY
 * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
 */
	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);

	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_16M, 1);
	rtc_reset();
	return 0;
}


#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct tsec_info_struct tsec_info[4];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int num = 0;
	char *tmp;
	u32 pordevsr;
	unsigned int vscfw_addr;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	pordevsr = in_be32(&gur->pordevsr);
	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
	if ((tmp = getenv ("vscfw_addr")) != NULL) {
		vscfw_addr = simple_strtoul (tmp, NULL, 16);
		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
		if (vsc7385_upload_firmware((void *) vscfw_addr,
					CONFIG_VSC7385_IMAGE_SIZE))
			puts("Failure uploading VSC7385 microcode.\n");
	} else
		puts("No address specified for VSC7385 microcode.\n");
#endif

	tsec_eth_init(bis, tsec_info, num);

	return pci_eth_init(bis);
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_pci_board_setup(void *blob);

void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	ft_pci_board_setup(blob);

	fdt_fixup_memory(blob, (u64)base, (u64)size);
}
#endif

#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);

void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
728ece34	1	/*
39c2a6eb	2	* Copyright 2009-2010 Freescale Semiconductor, Inc.
728ece34 PA	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <asm/processor.h>
	26	#include <asm/mmu.h>
	27	#include <asm/cache.h>
	28	#include <asm/immap_85xx.h>
	29	#include <asm/io.h>
	30	#include <miiphy.h>
	31	#include <libfdt.h>
	32	#include <fdt_support.h>
	33	#include <tsec.h>
	34	#include <vsc7385.h>
	35	#include <netdev.h>
39c2a6eb	36	#include <rtc.h>
728ece34 PA	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	#define VSC7385_RST_SET 0x00080000
	41	#define SLIC_RST_SET 0x00040000
	42	#define SGMII_PHY_RST_SET 0x00020000
	43	#define PCIE_RST_SET 0x00010000
	44	#define RGMII_PHY_RST_SET 0x02000000
	45
	46	#define USB_RST_CLR 0x04000000
	47
	48	#define GPIO_DIR 0x060f0000
	49
	50	#define BOARD_PERI_RST_SET VSC7385_RST_SET \| SLIC_RST_SET \| \
	51	SGMII_PHY_RST_SET \| PCIE_RST_SET \| \
	52	RGMII_PHY_RST_SET
	53
	54	#define SYSCLK_MASK 0x00200000
	55	#define BOARDREV_MASK 0x10100000
	56	#define BOARDREV_B 0x10100000
	57	#define BOARDREV_C 0x00100000
75997dc5	58	#define BOARDREV_D 0x00000000
728ece34 PA	59
	60	#define SYSCLK_66 66666666
	61	#define SYSCLK_50 50000000
	62	#define SYSCLK_100 100000000
	63
	64	unsigned long get_board_sys_clk(ulong dummy)
	65	{
	66	volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	67	u32 val_gpdat, sysclk_gpio, board_rev_gpio;
	68
75997dc5	69	val_gpdat = in_be32(&pgpio->gpdat);
728ece34 PA	70	sysclk_gpio = val_gpdat & SYSCLK_MASK;
	71	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	72	if (board_rev_gpio == BOARDREV_C) {
	73	if(sysclk_gpio == 0)
	74	return SYSCLK_66;
	75	else
	76	return SYSCLK_100;
	77	} else if (board_rev_gpio == BOARDREV_B) {
	78	if(sysclk_gpio == 0)
	79	return SYSCLK_66;
	80	else
	81	return SYSCLK_50;
75997dc5 PA	82	} else if (board_rev_gpio == BOARDREV_D) {
	83	if(sysclk_gpio == 0)
	84	return SYSCLK_66;
	85	else
	86	return SYSCLK_100;
728ece34 PA	87	}
	88	return 0;
	89	}
	90
	91	#ifdef CONFIG_MMC
	92	int board_early_init_f (void)
	93	{
	94	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	95
	96	setbits_be32(&gur->pmuxcr,
	97	(MPC85xx_PMUXCR_SDHC_CD \|
	98	MPC85xx_PMUXCR_SDHC_WP));
	99	return 0;
	100	}
	101	#endif
	102
	103	int checkboard (void)
	104	{
	105	u32 val_gpdat, board_rev_gpio;
	106	volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	107	char board_rev = 0;
	108	struct cpu_type *cpu;
	109
75997dc5	110	val_gpdat = in_be32(&pgpio->gpdat);
728ece34 PA	111	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	112	if (board_rev_gpio == BOARDREV_C)
	113	board_rev = 'C';
	114	else if (board_rev_gpio == BOARDREV_B)
	115	board_rev = 'B';
75997dc5 PA	116	else if (board_rev_gpio == BOARDREV_D)
75997dc5 PA	117	board_rev = 'D';
728ece34 PA	118	else
	119	panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
	120
	121	cpu = gd->cpu;
	122	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
	123	setbits_be32(&pgpio->gpdir, GPIO_DIR);
	124
	125	/*
	126	* Bringing the following peripherals out of reset via GPIOs
	127	* 0 = reset and 1 = out of reset
	128	* GPIO12 - Reset to Ethernet Switch
	129	* GPIO13 - Reset to SLIC/SLAC devices
	130	* GPIO14 - Reset to SGMII_PHY_N
	131	* GPIO15 - Reset to PCIe slots
	132	* GPIO6 - Reset to RGMII PHY
	133	* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
	134	*/
	135	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
	136
	137	return 0;
	138	}
	139
	140	int board_early_init_r(void)
	141	{
	142	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
5fb6ea3a	143	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
728ece34 PA	144
	145	/*
	146	* Remap Boot flash region to caching-inhibited
	147	* so that flash can be erased properly.
	148	*/
	149
	150	/* Flush d-cache and invalidate i-cache of any FLASH data */
	151	flush_dcache();
	152	invalidate_icache();
	153
	154	/* invalidate existing TLB entry for flash */
	155	disable_tlb(flash_esel);
	156
	157	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	158	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	159	0, flash_esel, BOOKE_PAGESZ_16M, 1);
39c2a6eb	160	rtc_reset();
728ece34 PA	161	return 0;
	162	}
	163
	164
	165	#ifdef CONFIG_TSEC_ENET
	166	int board_eth_init(bd_t *bis)
	167	{
	168	struct tsec_info_struct tsec_info[4];
	169	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	170	int num = 0;
	171	char *tmp;
75997dc5	172	u32 pordevsr;
728ece34 PA	173	unsigned int vscfw_addr;
	174
	175	#ifdef CONFIG_TSEC1
	176	SET_STD_TSEC_INFO(tsec_info[num], 1);
	177	num++;
	178	#endif
	179	#ifdef CONFIG_TSEC2
	180	SET_STD_TSEC_INFO(tsec_info[num], 2);
	181	num++;
	182	#endif
	183	#ifdef CONFIG_TSEC3
	184	SET_STD_TSEC_INFO(tsec_info[num], 3);
75997dc5 PA	185	pordevsr = in_be32(&gur->pordevsr);
75997dc5 PA	186	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
728ece34 PA	187	tsec_info[num].flags \|= TSEC_SGMII;
	188	num++;
	189	#endif
	190	if (!num) {
	191	printf("No TSECs initialized\n");
	192	return 0;
	193	}
	194	#ifdef CONFIG_VSC7385_ENET
	195	/* If a VSC7385 microcode image is present, then upload it. */
	196	if ((tmp = getenv ("vscfw_addr")) != NULL) {
	197	vscfw_addr = simple_strtoul (tmp, NULL, 16);
	198	printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
	199	if (vsc7385_upload_firmware((void *) vscfw_addr,
	200	CONFIG_VSC7385_IMAGE_SIZE))
	201	puts("Failure uploading VSC7385 microcode.\n");
	202	} else
	203	puts("No address specified for VSC7385 microcode.\n");
	204	#endif
	205
	206	tsec_eth_init(bis, tsec_info, num);
	207
	208	return pci_eth_init(bis);
	209	}
	210	#endif
	211
	212	#if defined(CONFIG_OF_BOARD_SETUP)
1749c3da KG	213	extern void ft_pci_board_setup(void *blob);
1749c3da KG	214
728ece34 PA	215	void ft_board_setup(void blob, bd_t bd)
	216	{
	217	phys_addr_t base;
	218	phys_size_t size;
	219
	220	ft_cpu_setup(blob, bd);
	221
	222	base = getenv_bootm_low();
	223	size = getenv_bootm_size();
	224
1749c3da KG	225	ft_pci_board_setup(blob);
1749c3da KG	226
728ece34 PA	227	fdt_fixup_memory(blob, (u64)base, (u64)size);
	228	}
	229	#endif
	230
	231	#ifdef CONFIG_MP
	232	extern void cpu_mp_lmb_reserve(struct lmb *lmb);
	233
	234	void board_lmb_reserve(struct lmb *lmb)
	235	{
	236	cpu_mp_lmb_reserve(lmb);
	237	}
	238	#endif