[people/ms/u-boot.git] / board / freescale / p1_p2_rdb / p1_p2_rdb.c

/*
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <vsc7385.h>
#include <netdev.h>
#include <rtc.h>
#include <i2c.h>

DECLARE_GLOBAL_DATA_PTR;

#define VSC7385_RST_SET		0x00080000
#define SLIC_RST_SET		0x00040000
#define SGMII_PHY_RST_SET	0x00020000
#define PCIE_RST_SET		0x00010000
#define RGMII_PHY_RST_SET	0x02000000

#define USB_RST_CLR		0x04000000
#define USB2_PORT_OUT_EN        0x01000000

#define GPIO_DIR		0x060f0000

#define BOARD_PERI_RST_SET	VSC7385_RST_SET | SLIC_RST_SET | \
				SGMII_PHY_RST_SET | PCIE_RST_SET | \
				RGMII_PHY_RST_SET

#define SYSCLK_MASK	0x00200000
#define BOARDREV_MASK	0x10100000
#define BOARDREV_C	0x00100000
#define BOARDREV_D	0x00000000

#define SYSCLK_66	66666666
#define SYSCLK_100	100000000

unsigned long get_board_sys_clk(ulong dummy)
{
	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val_gpdat, sysclk_gpio;

	val_gpdat = in_be32(&pgpio->gpdat);
	sysclk_gpio = val_gpdat & SYSCLK_MASK;

	if(sysclk_gpio == 0)
		return SYSCLK_66;
	else
		return SYSCLK_100;

	return 0;
}

#ifdef CONFIG_MMC
int board_early_init_f (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->pmuxcr,
			(MPC85xx_PMUXCR_SDHC_CD |
			 MPC85xx_PMUXCR_SDHC_WP));
	return 0;
}
#endif

int checkboard (void)
{
	u32 val_gpdat, board_rev_gpio;
	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	char board_rev = 0;
	struct cpu_type *cpu;

	val_gpdat = in_be32(&pgpio->gpdat);
	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	if (board_rev_gpio == BOARDREV_C)
		board_rev = 'C';
	else if (board_rev_gpio == BOARDREV_D)
		board_rev = 'D';
	else
		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);

	cpu = gd->cpu;
	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
#ifdef CONFIG_PHYS_64BIT
	puts ("(36-bit addrmap) \n");
#endif
	setbits_be32(&pgpio->gpdir, GPIO_DIR);

/*
 * Bringing the following peripherals out of reset via GPIOs
 * 0 = reset and 1 = out of reset
 * GPIO12 - Reset to Ethernet Switch
 * GPIO13 - Reset to SLIC/SLAC devices
 * GPIO14 - Reset to SGMII_PHY_N
 * GPIO15 - Reset to PCIe slots
 * GPIO6  - Reset to RGMII PHY
 * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
 */
	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);

	return 0;
}

int misc_init_r(void)
{
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;

	setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
	setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
#endif
	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	unsigned int orig_bus = i2c_get_bus_num();
	u8 i2c_data;

	i2c_set_bus_num(1);
	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
		1, &i2c_data, sizeof(i2c_data)) == 0) {
		if (i2c_data & 0x2)
			puts("NOR Flash Bank : Secondary\n");
		else
			puts("NOR Flash Bank : Primary\n");

		if (i2c_data & 0x1) {
			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
			puts("SD/MMC : 8-bit Mode\n");
			puts("eSPI : Disabled\n");
		} else {
			puts("SD/MMC : 4-bit Mode\n");
			puts("eSPI : Enabled\n");
		}
	} else {
		puts("Failed reading I2C Chip 0x18 on bus 1\n");
	}
	i2c_set_bus_num(orig_bus);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_16M, 1);
	rtc_reset();
	return 0;
}


#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	int num = 0;
	char *tmp;
	unsigned int vscfw_addr;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
	if ((tmp = getenv ("vscfw_addr")) != NULL) {
		vscfw_addr = simple_strtoul (tmp, NULL, 16);
		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
		if (vsc7385_upload_firmware((void *) vscfw_addr,
					CONFIG_VSC7385_IMAGE_SIZE))
			puts("Failure uploading VSC7385 microcode.\n");
	} else
		puts("No address specified for VSC7385 microcode.\n");
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);

	return pci_eth_init(bis);
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_pci_board_setup(void *blob);

void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

#if defined(CONFIG_PCI)
	ft_pci_board_setup(blob);
#endif /* #if defined(CONFIG_PCI) */

	fdt_fixup_memory(blob, (u64)base, (u64)size);
}
#endif
Commit	Line	Data
728ece34	1	/*
b7070904	2	* Copyright 2009-2011 Freescale Semiconductor, Inc.
728ece34 PA	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <asm/processor.h>
	26	#include <asm/mmu.h>
	27	#include <asm/cache.h>
	28	#include <asm/immap_85xx.h>
058d7dc7	29	#include <asm/fsl_serdes.h>
728ece34 PA	30	#include <asm/io.h>
	31	#include <miiphy.h>
	32	#include <libfdt.h>
	33	#include <fdt_support.h>
063c1263	34	#include <fsl_mdio.h>
728ece34 PA	35	#include <tsec.h>
	36	#include <vsc7385.h>
	37	#include <netdev.h>
39c2a6eb	38	#include <rtc.h>
cac29f25	39	#include <i2c.h>
728ece34 PA	40
	41	DECLARE_GLOBAL_DATA_PTR;
	42
	43	#define VSC7385_RST_SET 0x00080000
	44	#define SLIC_RST_SET 0x00040000
	45	#define SGMII_PHY_RST_SET 0x00020000
	46	#define PCIE_RST_SET 0x00010000
	47	#define RGMII_PHY_RST_SET 0x02000000
	48
	49	#define USB_RST_CLR 0x04000000
2bad42a0	50	#define USB2_PORT_OUT_EN 0x01000000
728ece34 PA	51
	52	#define GPIO_DIR 0x060f0000
	53
	54	#define BOARD_PERI_RST_SET VSC7385_RST_SET \| SLIC_RST_SET \| \
	55	SGMII_PHY_RST_SET \| PCIE_RST_SET \| \
	56	RGMII_PHY_RST_SET
	57
	58	#define SYSCLK_MASK 0x00200000
	59	#define BOARDREV_MASK 0x10100000
728ece34	60	#define BOARDREV_C 0x00100000
75997dc5	61	#define BOARDREV_D 0x00000000
728ece34 PA	62
728ece34 PA	63	#define SYSCLK_66 66666666
728ece34 PA	64	#define SYSCLK_100 100000000
	65
	66	unsigned long get_board_sys_clk(ulong dummy)
	67	{
	68	volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
3313b20b	69	u32 val_gpdat, sysclk_gpio;
728ece34	70
75997dc5	71	val_gpdat = in_be32(&pgpio->gpdat);
728ece34	72	sysclk_gpio = val_gpdat & SYSCLK_MASK;
3313b20b PA	73
	74	if(sysclk_gpio == 0)
	75	return SYSCLK_66;
	76	else
	77	return SYSCLK_100;
	78
728ece34 PA	79	return 0;
	80	}
	81
	82	#ifdef CONFIG_MMC
	83	int board_early_init_f (void)
	84	{
	85	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	86
	87	setbits_be32(&gur->pmuxcr,
	88	(MPC85xx_PMUXCR_SDHC_CD \|
	89	MPC85xx_PMUXCR_SDHC_WP));
	90	return 0;
	91	}
	92	#endif
	93
	94	int checkboard (void)
	95	{
	96	u32 val_gpdat, board_rev_gpio;
	97	volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	98	char board_rev = 0;
	99	struct cpu_type *cpu;
	100
75997dc5	101	val_gpdat = in_be32(&pgpio->gpdat);
728ece34 PA	102	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	103	if (board_rev_gpio == BOARDREV_C)
	104	board_rev = 'C';
75997dc5 PA	105	else if (board_rev_gpio == BOARDREV_D)
75997dc5 PA	106	board_rev = 'D';
728ece34 PA	107	else
	108	panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
	109
	110	cpu = gd->cpu;
	111	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
e0082f7c PA	112	#ifdef CONFIG_PHYS_64BIT
	113	puts ("(36-bit addrmap) \n");
	114	#endif
728ece34 PA	115	setbits_be32(&pgpio->gpdir, GPIO_DIR);
	116
	117	/*
	118	* Bringing the following peripherals out of reset via GPIOs
	119	* 0 = reset and 1 = out of reset
	120	* GPIO12 - Reset to Ethernet Switch
	121	* GPIO13 - Reset to SLIC/SLAC devices
	122	* GPIO14 - Reset to SGMII_PHY_N
	123	* GPIO15 - Reset to PCIe slots
	124	* GPIO6 - Reset to RGMII PHY
	125	* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
	126	*/
	127	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
	128
	129	return 0;
	130	}
	131
2bad42a0 RM	132	int misc_init_r(void)
	133	{
	134	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	135	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	136	ccsr_gpio_t gpio = (void )CONFIG_SYS_MPC85xx_GPIO_ADDR;
	137
	138	setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
	139	setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
	140	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
	141	#endif
	142	return 0;
	143	}
	144
728ece34 PA	145	int board_early_init_r(void)
	146	{
	147	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
5fb6ea3a	148	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
cac29f25 PJ	149	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	150	unsigned int orig_bus = i2c_get_bus_num();
	151	u8 i2c_data;
	152
	153	i2c_set_bus_num(1);
	154	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
	155	1, &i2c_data, sizeof(i2c_data)) == 0) {
	156	if (i2c_data & 0x2)
	157	puts("NOR Flash Bank : Secondary\n");
	158	else
	159	puts("NOR Flash Bank : Primary\n");
	160
	161	if (i2c_data & 0x1) {
	162	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
	163	puts("SD/MMC : 8-bit Mode\n");
	164	puts("eSPI : Disabled\n");
	165	} else {
	166	puts("SD/MMC : 4-bit Mode\n");
	167	puts("eSPI : Enabled\n");
	168	}
	169	} else {
	170	puts("Failed reading I2C Chip 0x18 on bus 1\n");
	171	}
	172	i2c_set_bus_num(orig_bus);
728ece34 PA	173
	174	/*
	175	* Remap Boot flash region to caching-inhibited
	176	* so that flash can be erased properly.
	177	*/
	178
	179	/* Flush d-cache and invalidate i-cache of any FLASH data */
	180	flush_dcache();
	181	invalidate_icache();
	182
	183	/* invalidate existing TLB entry for flash */
	184	disable_tlb(flash_esel);
	185
	186	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	187	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	188	0, flash_esel, BOOKE_PAGESZ_16M, 1);
39c2a6eb	189	rtc_reset();
728ece34 PA	190	return 0;
	191	}
	192
	193
	194	#ifdef CONFIG_TSEC_ENET
	195	int board_eth_init(bd_t *bis)
	196	{
063c1263	197	struct fsl_pq_mdio_info mdio_info;
728ece34	198	struct tsec_info_struct tsec_info[4];
728ece34 PA	199	int num = 0;
	200	char *tmp;
	201	unsigned int vscfw_addr;
	202
	203	#ifdef CONFIG_TSEC1
	204	SET_STD_TSEC_INFO(tsec_info[num], 1);
	205	num++;
	206	#endif
	207	#ifdef CONFIG_TSEC2
	208	SET_STD_TSEC_INFO(tsec_info[num], 2);
	209	num++;
	210	#endif
	211	#ifdef CONFIG_TSEC3
	212	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	213	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	214	puts("eTSEC3 is in sgmii mode.\n");
728ece34	215	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	216	}
728ece34 PA	217	num++;
	218	#endif
	219	if (!num) {
	220	printf("No TSECs initialized\n");
	221	return 0;
	222	}
	223	#ifdef CONFIG_VSC7385_ENET
	224	/* If a VSC7385 microcode image is present, then upload it. */
	225	if ((tmp = getenv ("vscfw_addr")) != NULL) {
	226	vscfw_addr = simple_strtoul (tmp, NULL, 16);
	227	printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
	228	if (vsc7385_upload_firmware((void *) vscfw_addr,
	229	CONFIG_VSC7385_IMAGE_SIZE))
	230	puts("Failure uploading VSC7385 microcode.\n");
	231	} else
	232	puts("No address specified for VSC7385 microcode.\n");
	233	#endif
	234
063c1263 AF	235	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	236	mdio_info.name = DEFAULT_MII_NAME;
	237	fsl_pq_mdio_init(bis, &mdio_info);
	238
728ece34 PA	239	tsec_eth_init(bis, tsec_info, num);
	240
	241	return pci_eth_init(bis);
	242	}
	243	#endif
	244
	245	#if defined(CONFIG_OF_BOARD_SETUP)
1749c3da KG	246	extern void ft_pci_board_setup(void *blob);
1749c3da KG	247
728ece34 PA	248	void ft_board_setup(void blob, bd_t bd)
	249	{
	250	phys_addr_t base;
	251	phys_size_t size;
	252
	253	ft_cpu_setup(blob, bd);
	254
	255	base = getenv_bootm_low();
	256	size = getenv_bootm_size();
	257
b7070904	258	#if defined(CONFIG_PCI)
1749c3da	259	ft_pci_board_setup(blob);
b7070904	260	#endif /* #if defined(CONFIG_PCI) */
1749c3da	261
728ece34 PA	262	fdt_fixup_memory(blob, (u64)base, (u64)size);
	263	}
	264	#endif