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Commit | Line | Data |
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feb7838f | 1 | /* |
1ac63e40 | 2 | * Copyright 2008-2011 Freescale Semiconductor, Inc. |
feb7838f SS |
3 | * |
4 | * (C) Copyright 2000 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
feb7838f SS |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/mmu.h> | |
12 | ||
13 | struct fsl_e_tlb_entry tlb_table[] = { | |
14 | /* TLB 0 - for temp stack in cache */ | |
d51cc7a0 | 15 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
feb7838f SS |
16 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
17 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
18 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
d51cc7a0 | 19 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
feb7838f SS |
20 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
21 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
22 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
d51cc7a0 | 23 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
feb7838f SS |
24 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
25 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
26 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
d51cc7a0 | 27 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
feb7838f SS |
28 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
29 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
30 | ||
31 | /* TLB 1 */ | |
32 | /* *I*** - Covers boot page */ | |
33 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, | |
abc76eb6 | 34 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
feb7838f SS |
35 | 0, 0, BOOKE_PAGESZ_4K, 1), |
36 | ||
37 | /* *I*G* - CCSRBAR */ | |
38 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
39 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
40 | 0, 1, BOOKE_PAGESZ_1M, 1), | |
41 | ||
42 | /* W**G* - Flash/promjet, localbus */ | |
43 | /* This will be changed to *I*G* after relocation to RAM. */ | |
44 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, | |
45 | MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, | |
46 | 0, 2, BOOKE_PAGESZ_256M, 1), | |
47 | ||
48 | /* *I*G* - PCI */ | |
49 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, | |
50 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
51 | 0, 3, BOOKE_PAGESZ_1G, 1), | |
52 | ||
53 | /* *I*G* - PCI */ | |
54 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, | |
55 | CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, | |
56 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
57 | 0, 4, BOOKE_PAGESZ_256M, 1), | |
58 | ||
59 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, | |
60 | CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, | |
61 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
62 | 0, 5, BOOKE_PAGESZ_256M, 1), | |
63 | ||
64 | /* *I*G* - PCI I/O */ | |
65 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, | |
66 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
67 | 0, 6, BOOKE_PAGESZ_256K, 1), | |
68 | ||
69 | /* *I*G - NAND */ | |
70 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
71 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
72 | 0, 7, BOOKE_PAGESZ_1M, 1), | |
73 | ||
74 | SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, | |
75 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
76 | 0, 8, BOOKE_PAGESZ_4K, 1), | |
1ac63e40 JH |
77 | |
78 | #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) | |
79 | /* *I*G - L2SRAM */ | |
80 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, | |
81 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
82 | 0, 9, BOOKE_PAGESZ_256K, 1), | |
83 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, | |
84 | CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, | |
85 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
86 | 0, 10, BOOKE_PAGESZ_256K, 1), | |
87 | #endif | |
feb7838f SS |
88 | }; |
89 | ||
90 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |