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1 | /* |
2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * (C) Copyright 2000 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <asm/mmu.h> | |
28 | ||
29 | struct fsl_e_tlb_entry tlb_table[] = { | |
30 | /* TLB 0 - for temp stack in cache */ | |
31 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, | |
32 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
33 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
34 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
35 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
36 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
37 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
38 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
39 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
40 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
41 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
42 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
43 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
44 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
45 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
46 | ||
47 | /* TLB 1 */ | |
48 | /* *I*** - Covers boot page */ | |
49 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, | |
abc76eb6 | 50 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
feb7838f SS |
51 | 0, 0, BOOKE_PAGESZ_4K, 1), |
52 | ||
53 | /* *I*G* - CCSRBAR */ | |
54 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
55 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
56 | 0, 1, BOOKE_PAGESZ_1M, 1), | |
57 | ||
58 | /* W**G* - Flash/promjet, localbus */ | |
59 | /* This will be changed to *I*G* after relocation to RAM. */ | |
60 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, | |
61 | MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, | |
62 | 0, 2, BOOKE_PAGESZ_256M, 1), | |
63 | ||
64 | /* *I*G* - PCI */ | |
65 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, | |
66 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
67 | 0, 3, BOOKE_PAGESZ_1G, 1), | |
68 | ||
69 | /* *I*G* - PCI */ | |
70 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, | |
71 | CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, | |
72 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
73 | 0, 4, BOOKE_PAGESZ_256M, 1), | |
74 | ||
75 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, | |
76 | CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, | |
77 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
78 | 0, 5, BOOKE_PAGESZ_256M, 1), | |
79 | ||
80 | /* *I*G* - PCI I/O */ | |
81 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, | |
82 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
83 | 0, 6, BOOKE_PAGESZ_256K, 1), | |
84 | ||
85 | /* *I*G - NAND */ | |
86 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
87 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
88 | 0, 7, BOOKE_PAGESZ_1M, 1), | |
89 | ||
90 | SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, | |
91 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
92 | 0, 8, BOOKE_PAGESZ_4K, 1), | |
93 | }; | |
94 | ||
95 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |