[people/ms/u-boot.git] / board / freescale / t102xqds / t102xqds.c

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	char buf[64];
	struct cpu_type *cpu = gd->arch.cpu;
	static const char *const freq[] = {"100", "125", "156.25", "100.0"};
	int clock;
	u8 sw = QIXIS_READ(arch);

	printf("Board: %sQDS, ", cpu->name);
	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);

#ifdef CONFIG_SDCARD
	puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
	puts("SPI\n");
#else
	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x8)
		puts("PromJet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else if (sw == 0x15)
		printf("IFC Card\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif

	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));

	puts("SERDES Reference: ");
	sw = QIXIS_READ(brdcfg[2]);
	clock = (sw >> 6) & 3;
	printf("Clock1=%sMHz ", freq[clock]);
	clock = (sw >> 4) & 3;
	printf("Clock2=%sMHz\n", freq[clock]);

	return 0;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

static int board_mux_lane_to_slot(void)
{
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_prtcl_s1;
	u8 brdcfg9;

	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;


	brdcfg9 = QIXIS_READ(brdcfg[9]);
	QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);

	switch (srds_prtcl_s1) {
	case 0:
		/* SerDes1 is not enabled */
		break;
	case 0xd5:
	case 0x5b:
	case 0x6b:
	case 0x77:
	case 0x6f:
	case 0x7f:
		QIXIS_WRITE(brdcfg[12], 0x8c);
		break;
	case 0x40:
		QIXIS_WRITE(brdcfg[12], 0xfc);
		break;
	case 0xd6:
	case 0x5a:
	case 0x6a:
	case 0x56:
		QIXIS_WRITE(brdcfg[12], 0x88);
		break;
	case 0x47:
		QIXIS_WRITE(brdcfg[12], 0xcc);
		break;
	case 0x46:
		QIXIS_WRITE(brdcfg[12], 0xc8);
		break;
	case 0x95:
	case 0x99:
		brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
		QIXIS_WRITE(brdcfg[9], brdcfg9);
		QIXIS_WRITE(brdcfg[12], 0x8c);
		break;
	case 0x116:
		QIXIS_WRITE(brdcfg[12], 0x00);
		break;
	case 0x115:
	case 0x119:
	case 0x129:
	case 0x12b:
		/* Aurora, PCIe, SGMII, SATA */
		QIXIS_WRITE(brdcfg[12], 0x04);
		break;
	default:
		printf("WARNING: unsupported for SerDes Protocol %d\n",
		       srds_prtcl_s1);
		return -1;
	}

	return 0;
}

#ifdef CONFIG_PPC_T1024
static void board_mux_setup(void)
{
	u8 brdcfg15;

	brdcfg15 = QIXIS_READ(brdcfg[15]);
	brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;

	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
		/* Route QE_TDM multiplexed signals to TDM Riser slot */
		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
		QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
		QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
			    ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
	} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
		/* to UCC (ProfiBus) interface */
		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
	} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
		/* to DVI (HDMI) encoder */
		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
	} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
		/* to DFP (LCD) encoder */
		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
			    BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
	}

	if (hwconfig_arg_cmp("adaptor", "sdxc"))
		/* Route SPI_CS multiplexed signals to SD slot */
		QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
			    ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
}
#endif

int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2; /* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash + promjet */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
	set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
	setup_portals();
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	board_mux_lane_to_slot();
	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_64:
		return 64000000;
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}
	return 66666666;
}

#define NUM_SRDS_PLL	2
int misc_init_r(void)
{
#ifdef CONFIG_PPC_T1024
	board_mux_setup();
#endif
	return 0;
}

void fdt_fixup_spi_mux(void *blob)
{
	int nodeoff = 0;

	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
		while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
			"eon,en25s64")) >= 0) {
			fdt_del_node(blob, nodeoff);
		}
	} else {
		/* remove tdm node */
		while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
			"maxim,ds26522")) >= 0) {
			fdt_del_node(blob, nodeoff);
		}
	}
}

int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCI
	pci_of_setup(blob, bd);
#endif

	fdt_fixup_liodn(blob);

#ifdef CONFIG_HAS_FSL_DR_USB
	fdt_fixup_dr_usb(blob, bd);
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
	fdt_fixup_board_enet(blob);
#endif
	fdt_fixup_spi_mux(blob);

	return 0;
}

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}

#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
	/* does not provide HW signals for power management */
	QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
	/* Disable MCKE isolation */
	gpio_set_value(2, 0);
	udelay(1);
}
#endif
Commit	Line	Data
aba80048 SL	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
	9	#include <i2c.h>
	10	#include <netdev.h>
	11	#include <linux/compiler.h>
	12	#include <asm/mmu.h>
	13	#include <asm/processor.h>
	14	#include <asm/cache.h>
	15	#include <asm/immap_85xx.h>
	16	#include <asm/fsl_law.h>
	17	#include <asm/fsl_serdes.h>
	18	#include <asm/fsl_portals.h>
	19	#include <asm/fsl_liodn.h>
	20	#include <fm_eth.h>
	21	#include <hwconfig.h>
	22	#include <asm/mpc85xx_gpio.h>
	23	#include "../common/qixis.h"
	24	#include "t102xqds.h"
	25	#include "t102xqds_qixis.h"
	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	int checkboard(void)
	30	{
	31	char buf[64];
	32	struct cpu_type *cpu = gd->arch.cpu;
	33	static const char *const freq[] = {"100", "125", "156.25", "100.0"};
	34	int clock;
	35	u8 sw = QIXIS_READ(arch);
	36
	37	printf("Board: %sQDS, ", cpu->name);
	38	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
	39	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	40
	41	#ifdef CONFIG_SDCARD
	42	puts("SD/MMC\n");
	43	#elif CONFIG_SPIFLASH
	44	puts("SPI\n");
	45	#else
	46	sw = QIXIS_READ(brdcfg[0]);
	47	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	48
	49	if (sw < 0x8)
	50	printf("vBank: %d\n", sw);
	51	else if (sw == 0x8)
	52	puts("PromJet\n");
	53	else if (sw == 0x9)
	54	puts("NAND\n");
	55	else if (sw == 0x15)
	56	printf("IFC Card\n");
	57	else
	58	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	59	#endif
	60
	61	printf("FPGA: v%d (%s), build %d",
	62	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	63	(int)qixis_read_minor());
	64	/* the timestamp string contains "\n" at the end */
65	printf(" on %s", qixis_read_time(buf));
66
67	puts("SERDES Reference: ");
68	sw = QIXIS_READ(brdcfg[2]);
69	clock = (sw >> 6) & 3;
70	printf("Clock1=%sMHz ", freq[clock]);
71	clock = (sw >> 4) & 3;
72	printf("Clock2=%sMHz\n", freq[clock]);
73
74	return 0;
75	}
76
77	int select_i2c_ch_pca9547(u8 ch)
78	{
79	int ret;
80
81	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
82	if (ret) {
83	puts("PCA: failed to select proper channel\n");
84	return ret;
85	}
86
87	return 0;
88	}
89
90	static int board_mux_lane_to_slot(void)
91	{
92	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93	u32 srds_prtcl_s1;
94	u8 brdcfg9;
95
96	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
97	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
98	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
99
100
101	brdcfg9 = QIXIS_READ(brdcfg[9]);
102	QIXIS_WRITE(brdcfg[9], brdcfg9 \| BRDCFG9_XFI_TX_DISABLE);
103
104	switch (srds_prtcl_s1) {
105	case 0:
106	/* SerDes1 is not enabled */
107	break;
108	case 0xd5:
109	case 0x5b:
110	case 0x6b:
111	case 0x77:
112	case 0x6f:
113	case 0x7f:
114	QIXIS_WRITE(brdcfg[12], 0x8c);
115	break;
116	case 0x40:
117	QIXIS_WRITE(brdcfg[12], 0xfc);
118	break;
119	case 0xd6:
120	case 0x5a:
121	case 0x6a:
122	case 0x56:
123	QIXIS_WRITE(brdcfg[12], 0x88);
124	break;
125	case 0x47:
126	QIXIS_WRITE(brdcfg[12], 0xcc);
127	break;
128	case 0x46:
129	QIXIS_WRITE(brdcfg[12], 0xc8);
130	break;
131	case 0x95:
132	case 0x99:
133	brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
134	QIXIS_WRITE(brdcfg[9], brdcfg9);
135	QIXIS_WRITE(brdcfg[12], 0x8c);
136	break;
137	case 0x116:
138	QIXIS_WRITE(brdcfg[12], 0x00);
139	break;
140	case 0x115:
141	case 0x119:
142	case 0x129:
143	case 0x12b:
144	/* Aurora, PCIe, SGMII, SATA */
145	QIXIS_WRITE(brdcfg[12], 0x04);
146	break;
147	default:
148	printf("WARNING: unsupported for SerDes Protocol %d\n",
149	srds_prtcl_s1);
150	return -1;
151	}
152
153	return 0;
154	}
155
156	#ifdef CONFIG_PPC_T1024
157	static void board_mux_setup(void)
158	{
159	u8 brdcfg15;
160
161	brdcfg15 = QIXIS_READ(brdcfg[15]);
162	brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
163
164	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
165	/* Route QE_TDM multiplexed signals to TDM Riser slot */
166	QIXIS_WRITE(brdcfg[15], brdcfg15 \| BRDCFG15_DIUSEL_TDM);
167	QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
355b3858 SL	168	QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
355b3858 SL	169	~BRDCFG5_SPIRTE_MASK) \| BRDCFG5_SPIRTE_TDM);
aba80048 SL	170	} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
	171	/* to UCC (ProfiBus) interface */
	172	QIXIS_WRITE(brdcfg[15], brdcfg15 \| BRDCFG15_DIUSEL_UCC);
	173	} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
	174	/* to DVI (HDMI) encoder */
	175	QIXIS_WRITE(brdcfg[15], brdcfg15 \| BRDCFG15_DIUSEL_HDMI);
	176	} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
	177	/* to DFP (LCD) encoder */
	178	QIXIS_WRITE(brdcfg[15], brdcfg15 \| BRDCFG15_LCDFM \|
	179	BRDCFG15_LCDPD \| BRDCFG15_DIUSEL_LCD);
	180	}
355b3858 SL	181
	182	if (hwconfig_arg_cmp("adaptor", "sdxc"))
	183	/* Route SPI_CS multiplexed signals to SD slot */
	184	QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
	185	~BRDCFG5_SPIRTE_MASK) \| BRDCFG5_SPIRTE_SDHC);
aba80048 SL	186	}
	187	#endif
	188
	189	int board_early_init_r(void)
	190	{
	191	#ifdef CONFIG_SYS_FLASH_BASE
	192	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	193	int flash_esel = find_tlb_idx((void *)flashbase, 1);
	194
	195	/*
	196	* Remap Boot flash + PROMJET region to caching-inhibited
	197	* so that flash can be erased properly.
	198	*/
	199
	200	/* Flush d-cache and invalidate i-cache of any FLASH data */
	201	flush_dcache();
	202	invalidate_icache();
	203
	204	if (flash_esel == -1) {
	205	/* very unlikely unless something is messed up */
	206	puts("Error: Could not find TLB for FLASH BASE\n");
	207	flash_esel = 2; /* give our best effort to continue */
	208	} else {
	209	/* invalidate existing TLB entry for flash + promjet */
	210	disable_tlb(flash_esel);
	211	}
	212
	213	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	214	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	215	0, flash_esel, BOOKE_PAGESZ_256M, 1);
	216	#endif
	217	set_liodns();
	218	#ifdef CONFIG_SYS_DPAA_QBMAN
	219	setup_portals();
	220	#endif
	221	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	222	board_mux_lane_to_slot();
	223	return 0;
	224	}
	225
	226	unsigned long get_board_sys_clk(void)
	227	{
	228	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	229
	230	switch (sysclk_conf & 0x0F) {
	231	case QIXIS_SYSCLK_64:
	232	return 64000000;
	233	case QIXIS_SYSCLK_83:
	234	return 83333333;
	235	case QIXIS_SYSCLK_100:
	236	return 100000000;
	237	case QIXIS_SYSCLK_125:
	238	return 125000000;
	239	case QIXIS_SYSCLK_133:
	240	return 133333333;
	241	case QIXIS_SYSCLK_150:
	242	return 150000000;
	243	case QIXIS_SYSCLK_160:
	244	return 160000000;
	245	case QIXIS_SYSCLK_166:
	246	return 166666666;
	247	}
	248	return 66666666;
	249	}
250
251	unsigned long get_board_ddr_clk(void)
252	{
253	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
254
255	switch ((ddrclk_conf & 0x30) >> 4) {
256	case QIXIS_DDRCLK_100:
257	return 100000000;
258	case QIXIS_DDRCLK_125:
259	return 125000000;
260	case QIXIS_DDRCLK_133:
261	return 133333333;
262	}
263	return 66666666;
264	}
265
266	#define NUM_SRDS_PLL 2
267	int misc_init_r(void)
268	{
269	#ifdef CONFIG_PPC_T1024
270	board_mux_setup();
271	#endif
272	return 0;
273	}
274
355b3858 SL	275	void fdt_fixup_spi_mux(void *blob)
	276	{
	277	int nodeoff = 0;
	278
	279	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
	280	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	281	"eon,en25s64")) >= 0) {
	282	fdt_del_node(blob, nodeoff);
	283	}
	284	} else {
	285	/* remove tdm node */
	286	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
	287	"maxim,ds26522")) >= 0) {
	288	fdt_del_node(blob, nodeoff);
	289	}
	290	}
	291	}
	292
aba80048 SL	293	int ft_board_setup(void blob, bd_t bd)
	294	{
	295	phys_addr_t base;
	296	phys_size_t size;
	297
	298	ft_cpu_setup(blob, bd);
	299
	300	base = getenv_bootm_low();
	301	size = getenv_bootm_size();
	302
	303	fdt_fixup_memory(blob, (u64)base, (u64)size);
	304
	305	#ifdef CONFIG_PCI
	306	pci_of_setup(blob, bd);
	307	#endif
	308
	309	fdt_fixup_liodn(blob);
	310
	311	#ifdef CONFIG_HAS_FSL_DR_USB
	312	fdt_fixup_dr_usb(blob, bd);
	313	#endif
	314
	315	#ifdef CONFIG_SYS_DPAA_FMAN
	316	fdt_fixup_fman_ethernet(blob);
	317	fdt_fixup_board_enet(blob);
	318	#endif
355b3858	319	fdt_fixup_spi_mux(blob);
aba80048 SL	320
	321	return 0;
	322	}
	323
	324	void qixis_dump_switch(void)
	325	{
	326	int i, nr_of_cfgsw;
	327
	328	QIXIS_WRITE(cms[0], 0x00);
	329	nr_of_cfgsw = QIXIS_READ(cms[1]);
	330
	331	puts("DIP switch settings dump:\n");
	332	for (i = 1; i <= nr_of_cfgsw; i++) {
	333	QIXIS_WRITE(cms[0], i);
	334	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	335	}
	336	}
	337
	338	#ifdef CONFIG_DEEP_SLEEP
	339	void board_mem_sleep_setup(void)
	340	{
	341	/* does not provide HW signals for power management */
	342	QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
	343	/* Disable MCKE isolation */
	344	gpio_set_value(2, 0);
	345	udelay(1);
	346	}
	347	#endif