[people/ms/u-boot.git] / board / freescale / t102xrdb / t102xrdb.c

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#ifdef CONFIG_TARGET_T1024RDB
#include "cpld.h"
#elif defined(CONFIG_TARGET_T1023RDB)
#include <i2c.h>
#include <mmc.h>
#endif
#include "../common/sleep.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_TARGET_T1023RDB
enum {
	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
	GPIO1_EMMC_SEL,
	GPIO3_GET_VERSION,	       /* GPIO3_4/5, 00:RevB, 01: RevC */
	GPIO3_BRD_VER_MASK = 0x0c000000,
	GPIO3_OFFSET = 0x2000,
	I2C_GET_BANK,
	I2C_SET_BANK0,
	I2C_SET_BANK4,
};
#endif

int checkboard(void)
{
	struct cpu_type *cpu = gd->arch.cpu;
	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_s1;

	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;

	printf("Board: %sRDB, ", cpu->name);
#if defined(CONFIG_TARGET_T1024RDB)
	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
#elif defined(CONFIG_TARGET_T1023RDB)
	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
#endif
	printf("boot from ");

#ifdef CONFIG_SDCARD
	puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
	puts("SPI\n");
#elif defined(CONFIG_TARGET_T1024RDB)
	u8 reg;

	reg = CPLD_READ(flash_csr);

	if (reg & CPLD_BOOT_SEL) {
		puts("NAND\n");
	} else {
		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
		printf("NOR vBank%d\n", reg);
	}
#elif defined(CONFIG_TARGET_T1023RDB)
#ifdef CONFIG_NAND
	puts("NAND\n");
#else
	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
#endif
#endif

	puts("SERDES Reference Clocks:\n");
	if (srds_s1 == 0x95)
		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
	else
		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);

	return 0;
}

#ifdef CONFIG_TARGET_T1024RDB
static void board_mux_lane(void)
{
	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_prtcl_s1;
	u8 reg = CPLD_READ(misc_ctl_status);

	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;

	if (srds_prtcl_s1 == 0x95) {
		/* Route Lane B to PCIE */
		CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
	} else {
		/* Route Lane B to SGMII */
		CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
	}
	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
}
#endif

int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
	if (is_warm_boot())
		fsl_dp_disable_console();
#endif

	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);
	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();
	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash + promjet */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif

#ifdef CONFIG_TARGET_T1024RDB
	board_mux_lane();
#endif

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	return CONFIG_SYS_CLK_FREQ;
}

unsigned long get_board_ddr_clk(void)
{
	return CONFIG_DDR_CLK_FREQ;
}

int misc_init_r(void)
{
	return 0;
}

int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCI
	pci_of_setup(blob, bd);
#endif

	fdt_fixup_liodn(blob);
	fsl_fdt_fixup_dr_usb(blob, bd);

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
	fdt_fixup_board_enet(blob);
#endif

#ifdef CONFIG_TARGET_T1023RDB
	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
		fdt_enable_nor(blob);
#endif

	return 0;
}

#ifdef CONFIG_TARGET_T1023RDB
/* Enable NOR flash for RevC */
static void fdt_enable_nor(void *blob)
{
	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");

	if (nodeoff >= 0)
		fdt_status_okay(blob, nodeoff);
	else
		printf("WARNING unable to set status for NOR\n");
}

int board_mmc_getcd(struct mmc *mmc)
{
	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val = in_be32(&pgpio->gpdat);

	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
	val &= GPIO1_SD_SEL;

	return val ? -1 : 1;
}

int board_mmc_getwp(struct mmc *mmc)
{
	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val = in_be32(&pgpio->gpdat);

	val &= GPIO1_SD_SEL;

	return val ? -1 : 0;
}

static u32 t1023rdb_ctrl(u32 ctrl_type)
{
	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 val, orig_bus = i2c_get_bus_num();
	u8 tmp;

	switch (ctrl_type) {
	case GPIO1_SD_SEL:
		val = in_be32(&pgpio->gpdat);
		val |= GPIO1_SD_SEL;
		out_be32(&pgpio->gpdat, val);
		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
		break;
	case GPIO1_EMMC_SEL:
		val = in_be32(&pgpio->gpdat);
		val &= ~GPIO1_SD_SEL;
		out_be32(&pgpio->gpdat, val);
		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
		break;
	case GPIO3_GET_VERSION:
		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
			 + GPIO3_OFFSET);
		val = in_be32(&pgpio->gpdat);
		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
			val = 0;
		return val;
	case I2C_GET_BANK:
		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
		i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
		tmp &= 0x7;
		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
		i2c_set_bus_num(orig_bus);
		return tmp;
	case I2C_SET_BANK0:
		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
		tmp = 0x0;
		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
		tmp = 0xf8;
		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
		/* asserting HRESET_REQ */
		out_be32(&gur->rstcr, 0x2);
		break;
	case I2C_SET_BANK4:
		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
		tmp = 0x1;
		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
		tmp = 0xf8;
		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
		out_be32(&gur->rstcr, 0x2);
		break;
	default:
		break;
	}
	return 0;
}

static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
		    char * const argv[])
{
	if (argc < 2)
		return CMD_RET_USAGE;
	if (!strcmp(argv[1], "bank0"))
		t1023rdb_ctrl(I2C_SET_BANK0);
	else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
		t1023rdb_ctrl(I2C_SET_BANK4);
	else if (!strcmp(argv[1], "sd"))
		t1023rdb_ctrl(GPIO1_SD_SEL);
	else if (!strcmp(argv[1], "emmc"))
		t1023rdb_ctrl(GPIO1_EMMC_SEL);
	else
		return CMD_RET_USAGE;
	return 0;
}

U_BOOT_CMD(
	switch, 2, 0, switch_cmd,
	"for bank0/bank4/sd/emmc switch control in runtime",
	"command (e.g. switch bank4)"
);
#endif
Commit	Line	Data
48c6f328 SL	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
	9	#include <i2c.h>
	10	#include <netdev.h>
	11	#include <linux/compiler.h>
	12	#include <asm/mmu.h>
	13	#include <asm/processor.h>
	14	#include <asm/immap_85xx.h>
	15	#include <asm/fsl_law.h>
	16	#include <asm/fsl_serdes.h>
48c6f328	17	#include <asm/fsl_liodn.h>
48c6f328 SL	18	#include <fm_eth.h>
48c6f328 SL	19	#include "t102xrdb.h"
960286b6	20	#ifdef CONFIG_TARGET_T1024RDB
48c6f328	21	#include "cpld.h"
9082405d	22	#elif defined(CONFIG_TARGET_T1023RDB)
ff7ea2d1 SL	23	#include <i2c.h>
ff7ea2d1 SL	24	#include <mmc.h>
e8a7f1c3	25	#endif
f49b8c1b	26	#include "../common/sleep.h"
48c6f328 SL	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
9082405d	30	#ifdef CONFIG_TARGET_T1023RDB
e8a7f1c3	31	enum {
ff7ea2d1	32	GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
e8a7f1c3	33	GPIO1_EMMC_SEL,
ff7ea2d1 SL	34	GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
	35	GPIO3_BRD_VER_MASK = 0x0c000000,
	36	GPIO3_OFFSET = 0x2000,
	37	I2C_GET_BANK,
	38	I2C_SET_BANK0,
	39	I2C_SET_BANK4,
e8a7f1c3 SL	40	};
	41	#endif
	42
48c6f328 SL	43	int checkboard(void)
	44	{
	45	struct cpu_type *cpu = gd->arch.cpu;
	46	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
e26416a3 SL	47	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	48	u32 srds_s1;
	49
	50	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	51	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
48c6f328 SL	52
48c6f328 SL	53	printf("Board: %sRDB, ", cpu->name);
960286b6	54	#if defined(CONFIG_TARGET_T1024RDB)
e8a7f1c3	55	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
48c6f328	56	CPLD_READ(hw_ver), CPLD_READ(sw_ver));
9082405d	57	#elif defined(CONFIG_TARGET_T1023RDB)
ff7ea2d1	58	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
e8a7f1c3 SL	59	#endif
e8a7f1c3 SL	60	printf("boot from ");
48c6f328 SL	61
	62	#ifdef CONFIG_SDCARD
	63	puts("SD/MMC\n");
	64	#elif CONFIG_SPIFLASH
	65	puts("SPI\n");
960286b6	66	#elif defined(CONFIG_TARGET_T1024RDB)
48c6f328 SL	67	u8 reg;
	68
	69	reg = CPLD_READ(flash_csr);
	70
	71	if (reg & CPLD_BOOT_SEL) {
	72	puts("NAND\n");
	73	} else {
	74	reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
	75	printf("NOR vBank%d\n", reg);
	76	}
9082405d	77	#elif defined(CONFIG_TARGET_T1023RDB)
e8a7f1c3 SL	78	#ifdef CONFIG_NAND
	79	puts("NAND\n");
	80	#else
ff7ea2d1	81	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
e8a7f1c3	82	#endif
48c6f328 SL	83	#endif
	84
	85	puts("SERDES Reference Clocks:\n");
e26416a3 SL	86	if (srds_s1 == 0x95)
	87	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
	88	else
e8a7f1c3	89	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
48c6f328 SL	90
	91	return 0;
	92	}
	93
960286b6	94	#ifdef CONFIG_TARGET_T1024RDB
e26416a3 SL	95	static void board_mux_lane(void)
	96	{
	97	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	98	u32 srds_prtcl_s1;
	99	u8 reg = CPLD_READ(misc_ctl_status);
	100
	101	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
	102	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	103	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
	104
	105	if (srds_prtcl_s1 == 0x95) {
	106	/* Route Lane B to PCIE */
	107	CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
	108	} else {
	109	/* Route Lane B to SGMII */
	110	CPLD_WRITE(misc_ctl_status, reg \| CPLD_PCIE_SGMII_MUX);
	111	}
	112	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
	113	}
e8a7f1c3	114	#endif
e26416a3	115
f49b8c1b	116	int board_early_init_f(void)
	117	{
	118	#if defined(CONFIG_DEEP_SLEEP)
	119	if (is_warm_boot())
	120	fsl_dp_disable_console();
	121	#endif
	122
	123	return 0;
	124	}
	125
48c6f328 SL	126	int board_early_init_r(void)
	127	{
	128	#ifdef CONFIG_SYS_FLASH_BASE
	129	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	130	int flash_esel = find_tlb_idx((void *)flashbase, 1);
	131	/*
	132	* Remap Boot flash region to caching-inhibited
	133	* so that flash can be erased properly.
	134	*/
	135
	136	/* Flush d-cache and invalidate i-cache of any FLASH data */
	137	flush_dcache();
	138	invalidate_icache();
	139	if (flash_esel == -1) {
	140	/* very unlikely unless something is messed up */
	141	puts("Error: Could not find TLB for FLASH BASE\n");
	142	flash_esel = 2; /* give our best effort to continue */
	143	} else {
	144	/* invalidate existing TLB entry for flash + promjet */
	145	disable_tlb(flash_esel);
	146	}
	147
	148	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	149	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	150	0, flash_esel, BOOKE_PAGESZ_256M, 1);
	151	#endif
	152
960286b6	153	#ifdef CONFIG_TARGET_T1024RDB
e26416a3	154	board_mux_lane();
e8a7f1c3	155	#endif
48c6f328 SL	156
	157	return 0;
	158	}
	159
	160	unsigned long get_board_sys_clk(void)
	161	{
	162	return CONFIG_SYS_CLK_FREQ;
	163	}
	164
	165	unsigned long get_board_ddr_clk(void)
	166	{
	167	return CONFIG_DDR_CLK_FREQ;
	168	}
	169
	170	int misc_init_r(void)
	171	{
	172	return 0;
	173	}
	174
	175	int ft_board_setup(void blob, bd_t bd)
	176	{
	177	phys_addr_t base;
	178	phys_size_t size;
	179
	180	ft_cpu_setup(blob, bd);
	181
	182	base = getenv_bootm_low();
	183	size = getenv_bootm_size();
	184
	185	fdt_fixup_memory(blob, (u64)base, (u64)size);
	186
	187	#ifdef CONFIG_PCI
	188	pci_of_setup(blob, bd);
	189	#endif
	190
	191	fdt_fixup_liodn(blob);
a5c289b9	192	fsl_fdt_fixup_dr_usb(blob, bd);
48c6f328 SL	193
	194	#ifdef CONFIG_SYS_DPAA_FMAN
	195	fdt_fixup_fman_ethernet(blob);
	196	fdt_fixup_board_enet(blob);
	197	#endif
	198
9082405d	199	#ifdef CONFIG_TARGET_T1023RDB
ff7ea2d1 SL	200	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
	201	fdt_enable_nor(blob);
	202	#endif
	203
48c6f328 SL	204	return 0;
48c6f328 SL	205	}
e8a7f1c3	206
9082405d	207	#ifdef CONFIG_TARGET_T1023RDB
ff7ea2d1 SL	208	/* Enable NOR flash for RevC */
ff7ea2d1 SL	209	static void fdt_enable_nor(void *blob)
e8a7f1c3	210	{
ff7ea2d1 SL	211	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
	212
	213	if (nodeoff >= 0)
	214	fdt_status_okay(blob, nodeoff);
	215	else
	216	printf("WARNING unable to set status for NOR\n");
	217	}
e8a7f1c3	218
ff7ea2d1 SL	219	int board_mmc_getcd(struct mmc *mmc)
	220	{
	221	ccsr_gpio_t __iomem pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	222	u32 val = in_be32(&pgpio->gpdat);
	223
	224	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
	225	val &= GPIO1_SD_SEL;
	226
	227	return val ? -1 : 1;
	228	}
	229
	230	int board_mmc_getwp(struct mmc *mmc)
	231	{
	232	ccsr_gpio_t __iomem pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	233	u32 val = in_be32(&pgpio->gpdat);
	234
	235	val &= GPIO1_SD_SEL;
	236
	237	return val ? -1 : 0;
	238	}
	239
	240	static u32 t1023rdb_ctrl(u32 ctrl_type)
	241	{
	242	ccsr_gpio_t __iomem pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	243	ccsr_gur_t __iomem gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	244	u32 val, orig_bus = i2c_get_bus_num();
	245	u8 tmp;
e8a7f1c3 SL	246
	247	switch (ctrl_type) {
	248	case GPIO1_SD_SEL:
ff7ea2d1 SL	249	val = in_be32(&pgpio->gpdat);
	250	val \|= GPIO1_SD_SEL;
	251	out_be32(&pgpio->gpdat, val);
	252	setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
e8a7f1c3 SL	253	break;
e8a7f1c3 SL	254	case GPIO1_EMMC_SEL:
ff7ea2d1 SL	255	val = in_be32(&pgpio->gpdat);
	256	val &= ~GPIO1_SD_SEL;
	257	out_be32(&pgpio->gpdat, val);
	258	setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
e8a7f1c3	259	break;
ff7ea2d1 SL	260	case GPIO3_GET_VERSION:
	261	pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
	262	+ GPIO3_OFFSET);
	263	val = in_be32(&pgpio->gpdat);
	264	val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
	265	if (val == 0x3) /* GPIO3_4/5 not used on RevB */
	266	val = 0;
	267	return val;
	268	case I2C_GET_BANK:
	269	i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
	270	i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
	271	tmp &= 0x7;
	272	tmp = ((tmp & 1) << 2) \| (tmp & 2) \| ((tmp & 4) >> 2);
	273	i2c_set_bus_num(orig_bus);
	274	return tmp;
	275	case I2C_SET_BANK0:
	276	i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
	277	tmp = 0x0;
	278	i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
	279	tmp = 0xf8;
	280	i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
	281	/* asserting HRESET_REQ */
	282	out_be32(&gur->rstcr, 0x2);
e8a7f1c3	283	break;
ff7ea2d1 SL	284	case I2C_SET_BANK4:
	285	i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
	286	tmp = 0x1;
	287	i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
	288	tmp = 0xf8;
	289	i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
	290	out_be32(&gur->rstcr, 0x2);
e8a7f1c3	291	break;
e8a7f1c3 SL	292	default:
	293	break;
	294	}
e8a7f1c3 SL	295	return 0;
	296	}
	297
ff7ea2d1	298	static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
e8a7f1c3 SL	299	char * const argv[])
	300	{
	301	if (argc < 2)
	302	return CMD_RET_USAGE;
ff7ea2d1 SL	303	if (!strcmp(argv[1], "bank0"))
	304	t1023rdb_ctrl(I2C_SET_BANK0);
	305	else if (!strcmp(argv[1], "bank4") \|\| !strcmp(argv[1], "altbank"))
	306	t1023rdb_ctrl(I2C_SET_BANK4);
e8a7f1c3	307	else if (!strcmp(argv[1], "sd"))
ff7ea2d1 SL	308	t1023rdb_ctrl(GPIO1_SD_SEL);
	309	else if (!strcmp(argv[1], "emmc"))
	310	t1023rdb_ctrl(GPIO1_EMMC_SEL);
e8a7f1c3 SL	311	else
	312	return CMD_RET_USAGE;
	313	return 0;
	314	}
	315
	316	U_BOOT_CMD(
ff7ea2d1 SL	317	switch, 2, 0, switch_cmd,
	318	"for bank0/bank4/sd/emmc switch control in runtime",
	319	"command (e.g. switch bank4)"
e8a7f1c3 SL	320	);
e8a7f1c3 SL	321	#endif