[people/ms/u-boot.git] / board / freescale / t104xrdb / ddr.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
#include "ddr.h"

DECLARE_GLOBAL_DATA_PTR;

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	ulong ddr_freq;

	if (ctrl_num > 1) {
		printf("Not supported controller number %d\n", ctrl_num);
		return;
	}
	if (!pdimm->n_ranks)
		return;

	pbsp = udimms[0];

	/* Get clk_adjust according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(0) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm->n_ranks &&
		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->clk_adjust = pbsp->clk_adjust;
				popts->wrlvl_start = pbsp->wrlvl_start;
				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found\n");
		printf("for data rate %lu MT/s\n", ddr_freq);
		printf("Trying to use the highest speed (%u) parameters\n",
		       pbsp_highest->datarate_mhz_high);
		popts->clk_adjust = pbsp_highest->clk_adjust;
		popts->wrlvl_start = pbsp_highest->wrlvl_start;
		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	} else {
		panic("DIMM is not supported by this board");
	}
found:
	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
		"wrlvl_ctrl_3 0x%x\n",
		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
		pbsp->wrlvl_ctl_3);

	/*
	 * Factors to consider for half-strength driver enable:
	 *	- number of DIMMs installed
	 */
#ifdef CONFIG_SYS_FSL_DDR4
	popts->half_strength_driver_enable = 1;
#else
	popts->half_strength_driver_enable = 0;
#endif
	/*
	 * Write leveling override
	 */
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;

	/*
	 * rtt and rtt_wr override
	 */
	popts->rtt_override = 0;

	/* Enable ZQ calibration */
	popts->zq_en = 1;

	/* DHC_EN =1, ODT = 75 Ohm */
#ifdef CONFIG_SYS_FSL_DDR4
	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
		DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
#else
	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
#endif
}

#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;

	/* does not provide HW signals for power management */
	clrbits_8(cpld_base + 0x17, 0x40);
	/* Disable MCKE isolation */
	gpio_set_value(2, 0);
	udelay(1);
}
#endif

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size;

#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
	puts("Initializing....using SPD\n");

	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

#else
	dram_size =  fsl_ddr_sdram_size();
#endif

#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
	fsl_dp_resume();
#endif

	return dram_size;
}
Commit	Line	Data
062ef1a6 PJ	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <hwconfig.h>
	10	#include <asm/mmu.h>
5614e71b YS	11	#include <fsl_ddr_sdram.h>
5614e71b YS	12	#include <fsl_ddr_dimm_params.h>
062ef1a6	13	#include <asm/fsl_law.h>
00233528	14	#include <asm/mpc85xx_gpio.h>
062ef1a6 PJ	15	#include "ddr.h"
	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
062ef1a6 PJ	19	void fsl_ddr_board_options(memctl_options_t *popts,
	20	dimm_params_t *pdimm,
	21	unsigned int ctrl_num)
	22	{
	23	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
	24	ulong ddr_freq;
	25
	26	if (ctrl_num > 1) {
	27	printf("Not supported controller number %d\n", ctrl_num);
	28	return;
	29	}
	30	if (!pdimm->n_ranks)
	31	return;
	32
	33	pbsp = udimms[0];
	34
96ac18c9	35	/* Get clk_adjust according to the board ddr
062ef1a6 PJ	36	* freqency and n_banks specified in board_specific_parameters table.
	37	*/
	38	ddr_freq = get_ddr_freq(0) / 1000000;
	39	while (pbsp->datarate_mhz_high) {
	40	if (pbsp->n_ranks == pdimm->n_ranks &&
	41	(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
	42	if (ddr_freq <= pbsp->datarate_mhz_high) {
062ef1a6 PJ	43	popts->clk_adjust = pbsp->clk_adjust;
	44	popts->wrlvl_start = pbsp->wrlvl_start;
	45	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	46	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
062ef1a6 PJ	47	goto found;
	48	}
	49	pbsp_highest = pbsp;
	50	}
	51	pbsp++;
	52	}
	53
	54	if (pbsp_highest) {
	55	printf("Error: board specific timing not found\n");
	56	printf("for data rate %lu MT/s\n", ddr_freq);
	57	printf("Trying to use the highest speed (%u) parameters\n",
	58	pbsp_highest->datarate_mhz_high);
062ef1a6 PJ	59	popts->clk_adjust = pbsp_highest->clk_adjust;
	60	popts->wrlvl_start = pbsp_highest->wrlvl_start;
	61	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	62	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
062ef1a6 PJ	63	} else {
	64	panic("DIMM is not supported by this board");
	65	}
	66	found:
	67	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
	68	"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
	69	"wrlvl_ctrl_3 0x%x\n",
	70	pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
	71	pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
	72	pbsp->wrlvl_ctl_3);
	73
	74	/*
	75	* Factors to consider for half-strength driver enable:
	76	* - number of DIMMs installed
	77	*/
4b6067ae PJ	78	#ifdef CONFIG_SYS_FSL_DDR4
	79	popts->half_strength_driver_enable = 1;
	80	#else
062ef1a6	81	popts->half_strength_driver_enable = 0;
4b6067ae	82	#endif
062ef1a6 PJ	83	/*
	84	* Write leveling override
	85	*/
	86	popts->wrlvl_override = 1;
	87	popts->wrlvl_sample = 0xf;
	88
	89	/*
	90	* rtt and rtt_wr override
	91	*/
	92	popts->rtt_override = 0;
	93
	94	/* Enable ZQ calibration */
	95	popts->zq_en = 1;
	96
	97	/* DHC_EN =1, ODT = 75 Ohm */
4b6067ae PJ	98	#ifdef CONFIG_SYS_FSL_DDR4
	99	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \| DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
	100	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) \|
	101	DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
	102	#else
92f7fed4 PJ	103	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
92f7fed4 PJ	104	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
4b6067ae	105	#endif
062ef1a6 PJ	106	}
062ef1a6 PJ	107
00233528 TY	108	#if defined(CONFIG_DEEP_SLEEP)
	109	void board_mem_sleep_setup(void)
	110	{
	111	void __iomem cpld_base = (void )CONFIG_SYS_CPLD_BASE;
	112
	113	/* does not provide HW signals for power management */
	114	clrbits_8(cpld_base + 0x17, 0x40);
	115	/* Disable MCKE isolation */
	116	gpio_set_value(2, 0);
	117	udelay(1);
	118	}
	119	#endif
	120
062ef1a6 PJ	121	phys_size_t initdram(int board_type)
	122	{
	123	phys_size_t dram_size;
	124
18c01445	125	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
062ef1a6 PJ	126	puts("Initializing....using SPD\n");
	127
	128	dram_size = fsl_ddr_sdram();
	129
	130	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	131	dram_size *= 0x100000;
	132
18c01445 PK	133	#else
	134	dram_size = fsl_ddr_sdram_size();
	135	#endif
00233528 TY	136
	137	#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
	138	fsl_dp_resume();
	139	#endif
	140
062ef1a6 PJ	141	return dram_size;
062ef1a6 PJ	142	}