[thirdparty/u-boot.git] / board / freescale / t104xrdb / eth.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fsl_dtsec.h>
#include <vsc9953.h>

#include "../common/fman.h"

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
	struct memac_mdio_info memac_mdio_info;
	unsigned int i;
	int phy_addr = 0;
#ifdef CONFIG_VSC9953
	phy_interface_t phy_int;
	struct mii_dev *bus;
#endif

	printf("Initializing Fman\n");

	memac_mdio_info.regs =
		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;

	/* Register the real 1G MDIO bus */
	fm_memac_mdio_init(bis, &memac_mdio_info);

	/*
	 * Program on board RGMII, SGMII PHY addresses.
	 */
	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
		int idx = i - FM1_DTSEC1;

		switch (fm_info_get_enet_if(i)) {
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
		case PHY_INTERFACE_MODE_SGMII:
			/* T1040RDB & T1040D4RDB only supports SGMII on
			 * DTSEC3
			 */
			fm_info_set_phy_address(FM1_DTSEC3,
						CONFIG_SYS_SGMII1_PHY_ADDR);
			break;
#endif
#ifdef CONFIG_TARGET_T1042RDB
		case PHY_INTERFACE_MODE_SGMII:
			/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
			if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
				fm_info_set_phy_address(i, 0);
			/* T1042RDB only supports SGMII on DTSEC3 */
			fm_info_set_phy_address(FM1_DTSEC3,
						CONFIG_SYS_SGMII1_PHY_ADDR);
			break;
#endif
#ifdef CONFIG_TARGET_T1042D4RDB
		case PHY_INTERFACE_MODE_SGMII:
			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
			 *  & DTSEC3
			 */
			if (FM1_DTSEC1 == i)
				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
			if (FM1_DTSEC2 == i)
				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
			if (FM1_DTSEC3 == i)
				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
			fm_info_set_phy_address(i, phy_addr);
			break;
#endif
		case PHY_INTERFACE_MODE_RGMII:
			if (FM1_DTSEC4 == i)
				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
			if (FM1_DTSEC5 == i)
				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
			fm_info_set_phy_address(i, phy_addr);
			break;
		case PHY_INTERFACE_MODE_QSGMII:
			fm_info_set_phy_address(i, 0);
			break;
		case PHY_INTERFACE_MODE_NONE:
			fm_info_set_phy_address(i, 0);
			break;
		default:
			printf("Fman1: DTSEC%u set to unknown interface %i\n",
			       idx + 1, fm_info_get_enet_if(i));
			fm_info_set_phy_address(i, 0);
			break;
		}
		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
		    fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
			fm_info_set_mdio(i, NULL);
		else
			fm_info_set_mdio(i,
					 miiphy_get_dev_by_name(
							DEFAULT_FM_MDIO_NAME));
	}

#ifdef CONFIG_VSC9953
	/* SerDes configured for QSGMII */
	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
		for (i = 0; i < 4; i++) {
			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
			phy_int = PHY_INTERFACE_MODE_QSGMII;

			vsc9953_port_info_set_mdio(i, bus);
			vsc9953_port_info_set_phy_address(i, phy_addr);
			vsc9953_port_info_set_phy_int(i, phy_int);
			vsc9953_port_enable(i);
		}
	}
	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
		for (i = 4; i < 8; i++) {
			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
			phy_int = PHY_INTERFACE_MODE_QSGMII;

			vsc9953_port_info_set_mdio(i, bus);
			vsc9953_port_info_set_phy_address(i, phy_addr);
			vsc9953_port_info_set_phy_int(i, phy_int);
			vsc9953_port_enable(i);
		}
	}

	/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
		vsc9953_port_enable(8);

	/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
		/* Enable L2 On MAC2 using SCFG */
		struct ccsr_scfg *scfg = (struct ccsr_scfg *)
				CONFIG_SYS_MPC85xx_SCFG;

		out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
			 (0x80000000));
		vsc9953_port_enable(9);
	}
#endif

	cpu_eth_init(bis);
#endif

	return pci_eth_init(bis);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
714fd406 PJ	2	/*
714fd406 PJ	3	* Copyright 2014 Freescale Semiconductor, Inc.
714fd406 PJ	4	*/
	5
	6	#include <common.h>
	7	#include <netdev.h>
db4a1767	8	#include <asm/fsl_serdes.h>
714fd406 PJ	9	#include <asm/immap_85xx.h>
	10	#include <fm_eth.h>
	11	#include <fsl_mdio.h>
	12	#include <malloc.h>
8225b2fd	13	#include <fsl_dtsec.h>
db4a1767	14	#include <vsc9953.h>
714fd406 PJ	15
	16	#include "../common/fman.h"
	17
	18	int board_eth_init(bd_t *bis)
	19	{
	20	#ifdef CONFIG_FMAN_ENET
	21	struct memac_mdio_info memac_mdio_info;
	22	unsigned int i;
	23	int phy_addr = 0;
db4a1767 CC	24	#ifdef CONFIG_VSC9953
	25	phy_interface_t phy_int;
	26	struct mii_dev *bus;
	27	#endif
	28
714fd406 PJ	29	printf("Initializing Fman\n");
	30
	31	memac_mdio_info.regs =
	32	(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
	33	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
	34
	35	/* Register the real 1G MDIO bus */
	36	fm_memac_mdio_init(bis, &memac_mdio_info);
	37
	38	/*
	39	* Program on board RGMII, SGMII PHY addresses.
	40	*/
	41	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
	42	int idx = i - FM1_DTSEC1;
	43
	44	switch (fm_info_get_enet_if(i)) {
6fcddd09	45	#if defined(CONFIG_TARGET_T1040RDB) \|\| defined(CONFIG_TARGET_T1040D4RDB)
714fd406	46	case PHY_INTERFACE_MODE_SGMII:
4b6067ae PJ	47	/* T1040RDB & T1040D4RDB only supports SGMII on
	48	* DTSEC3
	49	*/
714fd406 PJ	50	fm_info_set_phy_address(FM1_DTSEC3,
714fd406 PJ	51	CONFIG_SYS_SGMII1_PHY_ADDR);
b0615f0b	52	break;
363fb32a	53	#endif
0167369c	54	#ifdef CONFIG_TARGET_T1042RDB
363fb32a	55	case PHY_INTERFACE_MODE_SGMII:
	56	/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
	57	if ((FM1_DTSEC1 == i) \|\| (FM1_DTSEC2 == i))
	58	fm_info_set_phy_address(i, 0);
	59	/* T1042RDB only supports SGMII on DTSEC3 */
	60	fm_info_set_phy_address(FM1_DTSEC3,
	61	CONFIG_SYS_SGMII1_PHY_ADDR);
	62	break;
4b6067ae	63	#endif
319ed24a	64	#ifdef CONFIG_TARGET_T1042D4RDB
4b6067ae PJ	65	case PHY_INTERFACE_MODE_SGMII:
	66	/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
	67	* & DTSEC3
	68	*/
	69	if (FM1_DTSEC1 == i)
	70	phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
	71	if (FM1_DTSEC2 == i)
	72	phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
	73	if (FM1_DTSEC3 == i)
	74	phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
	75	fm_info_set_phy_address(i, phy_addr);
	76	break;
714fd406 PJ	77	#endif
	78	case PHY_INTERFACE_MODE_RGMII:
	79	if (FM1_DTSEC4 == i)
	80	phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
	81	if (FM1_DTSEC5 == i)
	82	phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
	83	fm_info_set_phy_address(i, phy_addr);
	84	break;
	85	case PHY_INTERFACE_MODE_QSGMII:
	86	fm_info_set_phy_address(i, 0);
	87	break;
	88	case PHY_INTERFACE_MODE_NONE:
	89	fm_info_set_phy_address(i, 0);
	90	break;
	91	default:
	92	printf("Fman1: DTSEC%u set to unknown interface %i\n",
	93	idx + 1, fm_info_get_enet_if(i));
	94	fm_info_set_phy_address(i, 0);
	95	break;
	96	}
9b478bef CC	97	if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII \|\|
	98	fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
	99	fm_info_set_mdio(i, NULL);
	100	else
	101	fm_info_set_mdio(i,
	102	miiphy_get_dev_by_name(
	103	DEFAULT_FM_MDIO_NAME));
714fd406 PJ	104	}
714fd406 PJ	105
db4a1767 CC	106	#ifdef CONFIG_VSC9953
	107	/* SerDes configured for QSGMII */
	108	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
	109	for (i = 0; i < 4; i++) {
	110	bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	111	phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
	112	phy_int = PHY_INTERFACE_MODE_QSGMII;
	113
	114	vsc9953_port_info_set_mdio(i, bus);
	115	vsc9953_port_info_set_phy_address(i, phy_addr);
	116	vsc9953_port_info_set_phy_int(i, phy_int);
	117	vsc9953_port_enable(i);
	118	}
	119	}
	120	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
	121	for (i = 4; i < 8; i++) {
	122	bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	123	phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
	124	phy_int = PHY_INTERFACE_MODE_QSGMII;
	125
	126	vsc9953_port_info_set_mdio(i, bus);
	127	vsc9953_port_info_set_phy_address(i, phy_addr);
	128	vsc9953_port_info_set_phy_int(i, phy_int);
	129	vsc9953_port_enable(i);
	130	}
	131	}
	132
	133	/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
	134	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
	135	vsc9953_port_enable(8);
	136
	137	/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
	138	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
	139	/* Enable L2 On MAC2 using SCFG */
	140	struct ccsr_scfg scfg = (struct ccsr_scfg )
	141	CONFIG_SYS_MPC85xx_SCFG;
	142
	143	out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) \|
	144	(0x80000000));
	145	vsc9953_port_enable(9);
	146	}
	147	#endif
	148
714fd406 PJ	149	cpu_eth_init(bis);
	150	#endif
	151
	152	return pci_eth_init(bis);
	153	}