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c4d0e811 SL |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 or later as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <i2c.h> | |
11 | #include <hwconfig.h> | |
12 | #include <asm/mmu.h> | |
13 | #include <fsl_ddr_sdram.h> | |
14 | #include <fsl_ddr_dimm_params.h> | |
15 | #include <asm/fsl_law.h> | |
16 | #include "ddr.h" | |
17 | ||
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
20 | void fsl_ddr_board_options(memctl_options_t *popts, | |
21 | dimm_params_t *pdimm, | |
22 | unsigned int ctrl_num) | |
23 | { | |
24 | const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; | |
25 | ulong ddr_freq; | |
26 | ||
3fdc827c | 27 | if (ctrl_num > 1) { |
c4d0e811 SL |
28 | printf("Not supported controller number %d\n", ctrl_num); |
29 | return; | |
30 | } | |
31 | if (!pdimm->n_ranks) | |
32 | return; | |
33 | ||
34 | /* | |
35 | * we use identical timing for all slots. If needed, change the code | |
36 | * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; | |
37 | */ | |
38 | if (popts->registered_dimm_en) | |
39 | pbsp = rdimms[0]; | |
40 | else | |
41 | pbsp = udimms[0]; | |
42 | ||
3fdc827c | 43 | /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr |
c4d0e811 SL |
44 | * freqency and n_banks specified in board_specific_parameters table. |
45 | */ | |
46 | ddr_freq = get_ddr_freq(0) / 1000000; | |
47 | while (pbsp->datarate_mhz_high) { | |
48 | if (pbsp->n_ranks == pdimm->n_ranks && | |
49 | (pdimm->rank_density >> 30) >= pbsp->rank_gb) { | |
50 | if (ddr_freq <= pbsp->datarate_mhz_high) { | |
c4d0e811 SL |
51 | popts->clk_adjust = pbsp->clk_adjust; |
52 | popts->wrlvl_start = pbsp->wrlvl_start; | |
53 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; | |
54 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; | |
c4d0e811 SL |
55 | goto found; |
56 | } | |
57 | pbsp_highest = pbsp; | |
58 | } | |
59 | pbsp++; | |
60 | } | |
61 | ||
62 | if (pbsp_highest) { | |
63 | printf("Error: board specific timing not found"); | |
64 | printf("for data rate %lu MT/s\n", ddr_freq); | |
65 | printf("Trying to use the highest speed (%u) parameters\n", | |
66 | pbsp_highest->datarate_mhz_high); | |
c4d0e811 SL |
67 | popts->clk_adjust = pbsp_highest->clk_adjust; |
68 | popts->wrlvl_start = pbsp_highest->wrlvl_start; | |
69 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; | |
70 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; | |
c4d0e811 SL |
71 | } else { |
72 | panic("DIMM is not supported by this board"); | |
73 | } | |
74 | found: | |
75 | debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" | |
76 | "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " | |
77 | "wrlvl_ctrl_3 0x%x\n", | |
78 | pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, | |
79 | pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, | |
80 | pbsp->wrlvl_ctl_3); | |
81 | ||
82 | /* | |
83 | * Factors to consider for half-strength driver enable: | |
84 | * - number of DIMMs installed | |
85 | */ | |
86 | popts->half_strength_driver_enable = 0; | |
87 | /* | |
88 | * Write leveling override | |
89 | */ | |
90 | popts->wrlvl_override = 1; | |
91 | popts->wrlvl_sample = 0xf; | |
92 | ||
93 | /* | |
94 | * Rtt and Rtt_WR override | |
95 | */ | |
96 | popts->rtt_override = 0; | |
97 | ||
98 | /* Enable ZQ calibration */ | |
99 | popts->zq_en = 1; | |
100 | ||
101 | /* DHC_EN =1, ODT = 75 Ohm */ | |
102 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); | |
103 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); | |
104 | } | |
105 | ||
106 | phys_size_t initdram(int board_type) | |
107 | { | |
108 | phys_size_t dram_size; | |
109 | ||
b19e288f | 110 | #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) |
c4d0e811 | 111 | puts("Initializing....using SPD\n"); |
c4d0e811 SL |
112 | dram_size = fsl_ddr_sdram(); |
113 | ||
114 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
115 | dram_size *= 0x100000; | |
b19e288f SL |
116 | #else |
117 | /* DDR has been initialised by first stage boot loader */ | |
118 | dram_size = fsl_ddr_sdram_size(); | |
119 | #endif | |
c4d0e811 | 120 | |
c4d0e811 SL |
121 | return dram_size; |
122 | } |