]>
Commit | Line | Data |
---|---|---|
f7f155e1 SL |
1 | # |
2 | # Copyright 2013 Freescale Semiconductor, Inc. | |
3 | # | |
4 | # SPDX-License-Identifier: GPL-2.0+ | |
5 | # | |
6 | # Refer doc/README.pblimage for more details about how-to configure | |
7 | # and create PBL boot image | |
8 | # | |
9 | ||
10 | #PBI commands | |
11 | #Initialize CPC1 | |
12 | 09010000 00200400 | |
13 | 09138000 00000000 | |
14 | 091380c0 00000100 | |
15 | #512KB SRAM | |
16 | 09010100 00000000 | |
17 | 09010104 fff80009 | |
18 | 09010f00 08000000 | |
19 | #enable CPC1 | |
20 | 09010000 80000000 | |
21 | #Configure LAW for CPC1 | |
22 | 09000d00 00000000 | |
23 | 09000d04 fff80000 | |
24 | 09000d08 81000012 | |
25 | #Initialize eSPI controller, default configuration is slow for eSPI to | |
26 | #load data, this configuration comes from u-boot eSPI driver. | |
27 | 09110000 80000403 | |
28 | 09110020 2d170008 | |
29 | 09110024 00100008 | |
30 | 09110028 00100008 | |
31 | 0911002c 00100008 | |
32 | #Errata for slowing down the MDC clock to make it <= 2.5 MHZ | |
33 | 094fc030 00008148 | |
34 | 094fd030 00008148 | |
35 | #Configure alternate space | |
36 | 09000010 00000000 | |
37 | 09000014 ff000000 | |
38 | 09000018 81000000 | |
39 | #Flush PBL data | |
c5938c10 | 40 | 091380c0 00100000 |