[people/ms/u-boot.git] / board / freescale / t208xrdb / cpld.h

/*
 * Copyright 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * CPLD register set of T2080RDB board-specific.
 */
struct cpld_data {
	u8 chip_id1;		/* 0x00 - Chip ID1 register */
	u8 chip_id2;		/* 0x01 - Chip ID2 register */
	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
	u8 sw_ver;		/* 0x03 - Software Revision register */
	u8 res0[12];		/* 0x04 - 0x0F - not used */
	u8 reset_ctl;		/* 0x10 - Reset control Register */
	u8 flash_csr;		/* 0x11 - Flash control and status register */
	u8 thermal_csr;		/* 0x12 - Thermal control and status register */
	u8 led_csr;		/* 0x13 - LED control and status register */
	u8 sfp_csr;		/* 0x14 - SFP+ control and status register */
	u8 misc_csr;		/* 0x15 - Misc control and status register */
	u8 boot_or;		/* 0x16 - Boot config override register */
	u8 boot_cfg1;		/* 0x17 - Boot configuration register 1 */
	u8 boot_cfg2;		/* 0x18 - Boot configuration register 2 */
} cpld_data_t;

u8 cpld_read(unsigned int reg);
void cpld_write(unsigned int reg, u8 value);

#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value)  \
	cpld_write(offsetof(struct cpld_data, reg), value)

/* CPLD on IFC */
#define CPLD_LBMAP_MASK		0x3F
#define CPLD_BANK_SEL_MASK	0x07
#define CPLD_BANK_OVERRIDE	0x40
#define CPLD_LBMAP_ALTBANK	0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK	0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET	0xFF
#define CPLD_LBMAP_SHIFT	0x03
#define CPLD_BOOT_SEL		0x80
Commit	Line	Data
8d67c368 SL	1	/*
	2	* Copyright 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	/*
	8	* CPLD register set of T2080RDB board-specific.
	9	*/
	10	struct cpld_data {
	11	u8 chip_id1; /* 0x00 - Chip ID1 register */
	12	u8 chip_id2; /* 0x01 - Chip ID2 register */
	13	u8 hw_ver; /* 0x02 - Hardware Revision Register */
	14	u8 sw_ver; /* 0x03 - Software Revision register */
	15	u8 res0[12]; /* 0x04 - 0x0F - not used */
	16	u8 reset_ctl; /* 0x10 - Reset control Register */
	17	u8 flash_csr; /* 0x11 - Flash control and status register */
	18	u8 thermal_csr; /* 0x12 - Thermal control and status register */
	19	u8 led_csr; /* 0x13 - LED control and status register */
	20	u8 sfp_csr; /* 0x14 - SFP+ control and status register */
	21	u8 misc_csr; /* 0x15 - Misc control and status register */
	22	u8 boot_or; /* 0x16 - Boot config override register */
	23	u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
	24	u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
	25	} cpld_data_t;
	26
	27	u8 cpld_read(unsigned int reg);
	28	void cpld_write(unsigned int reg, u8 value);
	29
	30	#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
	31	#define CPLD_WRITE(reg, value) \
	32	cpld_write(offsetof(struct cpld_data, reg), value)
	33
	34	/* CPLD on IFC */
	35	#define CPLD_LBMAP_MASK 0x3F
	36	#define CPLD_BANK_SEL_MASK 0x07
	37	#define CPLD_BANK_OVERRIDE 0x40
ef531c73 SL	38	#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR \| BANK 4 */
ef531c73 SL	39	#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR \| BANK 0 */
8d67c368 SL	40	#define CPLD_LBMAP_RESET 0xFF
	41	#define CPLD_LBMAP_SHIFT 0x03
	42	#define CPLD_BOOT_SEL 0x80