[people/ms/u-boot.git] / board / freescale / t4rdb / eth.c

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * Chunhe Lan <Chunhe.Lan@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>

#include "../common/fman.h"
#include "t4rdb.h"

void fdt_fixup_board_enet(void *fdt)
{
	return;
}

int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
	int i, interface;
	struct memac_mdio_info dtsec_mdio_info;
	struct memac_mdio_info tgec_mdio_info;
	struct mii_dev *dev;
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_prtcl_s1, srds_prtcl_s2;

	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;

	dtsec_mdio_info.regs =
		(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;

	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

	/* Register the 1G MDIO bus */
	fm_memac_mdio_init(bis, &dtsec_mdio_info);

	tgec_mdio_info.regs =
		(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;

	/* Register the 10G MDIO bus */
	fm_memac_mdio_init(bis, &tgec_mdio_info);

	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
		/* SGMII */
		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
		fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
		fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
	} else {
		puts("Invalid SerDes1 protocol for T4240RDB\n");
	}

	fm_disable_port(FM1_DTSEC5);
	fm_disable_port(FM1_DTSEC6);

	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
		interface = fm_info_get_enet_if(i);
		switch (interface) {
		case PHY_INTERFACE_MODE_SGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
		switch (fm_info_get_enet_if(i)) {
		case PHY_INTERFACE_MODE_XGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

#if (CONFIG_SYS_NUM_FMAN == 2)
	if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
		/* SGMII && XFI */
		fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
		fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
		fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
		fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
	} else {
		puts("Invalid SerDes2 protocol for T4240RDB\n");
	}

	fm_disable_port(FM2_DTSEC5);
	fm_disable_port(FM2_DTSEC6);
	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
		interface = fm_info_get_enet_if(i);
		switch (interface) {
		case PHY_INTERFACE_MODE_SGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
		switch (fm_info_get_enet_if(i)) {
		case PHY_INTERFACE_MODE_XGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}
#endif /* CONFIG_SYS_NUM_FMAN */

	cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */

	return pci_eth_init(bis);
}
Commit	Line	Data
0b2e13d9 CL	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* Chunhe Lan <Chunhe.Lan@freescale.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <command.h>
	11	#include <netdev.h>
	12	#include <asm/mmu.h>
	13	#include <asm/processor.h>
	14	#include <asm/cache.h>
	15	#include <asm/immap_85xx.h>
	16	#include <asm/fsl_law.h>
	17	#include <fsl_ddr_sdram.h>
	18	#include <asm/fsl_serdes.h>
	19	#include <asm/fsl_portals.h>
	20	#include <asm/fsl_liodn.h>
	21	#include <malloc.h>
	22	#include <fm_eth.h>
	23	#include <fsl_mdio.h>
	24	#include <miiphy.h>
	25	#include <phy.h>
8225b2fd	26	#include <fsl_dtsec.h>
0b2e13d9 CL	27	#include <asm/fsl_serdes.h>
	28	#include <hwconfig.h>
	29
	30	#include "../common/fman.h"
	31	#include "t4rdb.h"
	32
	33	void fdt_fixup_board_enet(void *fdt)
	34	{
	35	return;
	36	}
	37
	38	int board_eth_init(bd_t *bis)
	39	{
	40	#if defined(CONFIG_FMAN_ENET)
	41	int i, interface;
	42	struct memac_mdio_info dtsec_mdio_info;
	43	struct memac_mdio_info tgec_mdio_info;
	44	struct mii_dev *dev;
	45	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	46	u32 srds_prtcl_s1, srds_prtcl_s2;
	47
	48	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
	49	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	50	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
	51	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
	52	FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
	53	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
	54
	55	dtsec_mdio_info.regs =
	56	(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
	57
	58	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
	59
	60	/* Register the 1G MDIO bus */
	61	fm_memac_mdio_init(bis, &dtsec_mdio_info);
	62
	63	tgec_mdio_info.regs =
	64	(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
	65	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
	66
	67	/* Register the 10G MDIO bus */
	68	fm_memac_mdio_init(bis, &tgec_mdio_info);
	69
e6c334a7	70	if ((srds_prtcl_s1 == 28) \|\| (srds_prtcl_s1 == 27)) {
0b2e13d9 CL	71	/* SGMII */
	72	fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
	73	fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
	74	fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
	75	fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
	76	} else {
	77	puts("Invalid SerDes1 protocol for T4240RDB\n");
	78	}
	79
d1fc8ed4 YZ	80	fm_disable_port(FM1_DTSEC5);
	81	fm_disable_port(FM1_DTSEC6);
	82
0b2e13d9 CL	83	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
	84	interface = fm_info_get_enet_if(i);
	85	switch (interface) {
	86	case PHY_INTERFACE_MODE_SGMII:
	87	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	88	fm_info_set_mdio(i, dev);
	89	break;
	90	default:
	91	break;
	92	}
	93	}
	94
	95	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
	96	switch (fm_info_get_enet_if(i)) {
	97	case PHY_INTERFACE_MODE_XGMII:
	98	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	99	fm_info_set_mdio(i, dev);
	100	break;
	101	default:
	102	break;
	103	}
	104	}
	105
	106	#if (CONFIG_SYS_NUM_FMAN == 2)
3bcf047d	107	if ((srds_prtcl_s2 == 56) \|\| (srds_prtcl_s2 == 55)) {
0b2e13d9 CL	108	/* SGMII && XFI */
	109	fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
	110	fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
	111	fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
	112	fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
	113	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
	114	fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
	115	fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
	116	fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
	117	} else {
	118	puts("Invalid SerDes2 protocol for T4240RDB\n");
	119	}
	120
d1fc8ed4 YZ	121	fm_disable_port(FM2_DTSEC5);
d1fc8ed4 YZ	122	fm_disable_port(FM2_DTSEC6);
0b2e13d9 CL	123	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
	124	interface = fm_info_get_enet_if(i);
	125	switch (interface) {
	126	case PHY_INTERFACE_MODE_SGMII:
	127	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	128	fm_info_set_mdio(i, dev);
	129	break;
	130	default:
	131	break;
	132	}
	133	}
	134
	135	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
	136	switch (fm_info_get_enet_if(i)) {
	137	case PHY_INTERFACE_MODE_XGMII:
	138	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	139	fm_info_set_mdio(i, dev);
	140	break;
	141	default:
	142	break;
	143	}
	144	}
	145	#endif /* CONFIG_SYS_NUM_FMAN */
	146
	147	cpu_eth_init(bis);
	148	#endif /* CONFIG_FMAN_ENET */
	149
	150	return pci_eth_init(bis);
	151	}