projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ba91e26a WD |
1 | /* |
| 2 | * (C) Copyright 2004 | |
| 3 | * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) | |
| 4 | * | |
| 5 | * Support for the Elmeg VoVPN Gateway Module | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| ba91e26a WD |
8 | */ |
| 9 | ||
| 10 | #include <common.h> | |
| 11 | #include <ioports.h> | |
| 12 | #include <mpc8260.h> | |
| 13 | #include <asm/m8260_pci.h> | |
| 14 | #include <miiphy.h> | |
| 7aeda21a | 15 | #include <linux/compiler.h> |
| ba91e26a WD |
16 | |
| 17 | #include "m88e6060.h" | |
| 18 | ||
| 19 | /* | |
| 20 | * I/O Port configuration table | |
| 21 | * | |
| 22 | * if conf is 1, then that port pin will be configured at boot time | |
| 23 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
| 24 | */ | |
| 25 | ||
| 26 | const iop_conf_t iop_conf_tab[4][32] = { | |
| 27 | /* Port A configuration */ | |
| 28 | { /* conf ppar psor pdir podr pdat */ | |
| 29 | /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */ | |
| 30 | /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */ | |
| 31 | /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */ | |
| 32 | /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */ | |
| 33 | /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */ | |
| 34 | /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */ | |
| 35 | /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ | |
| 36 | /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ | |
| 37 | /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ | |
| 38 | /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ | |
| 39 | /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ | |
| 40 | /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */ | |
| 41 | /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */ | |
| 42 | /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */ | |
| 43 | /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */ | |
| 44 | /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */ | |
| 45 | /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */ | |
| 46 | /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */ | |
| 47 | /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */ | |
| 48 | /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */ | |
| 49 | /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */ | |
| 50 | /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */ | |
| 51 | /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ | |
| 52 | /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ | |
| 53 | /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 54 | /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 55 | /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 56 | /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 57 | /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 58 | /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 59 | /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ | |
| 60 | /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */ | |
| 61 | }, | |
| 62 | ||
| 63 | /* Port B configuration */ | |
| 64 | { /* conf ppar psor pdir podr pdat */ | |
| 65 | /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */ | |
| 66 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */ | |
| 67 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */ | |
| 68 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */ | |
| 69 | /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */ | |
| 70 | /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */ | |
| 71 | /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */ | |
| 72 | /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */ | |
| 73 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */ | |
| 74 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */ | |
| 75 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */ | |
| 76 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */ | |
| 77 | /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */ | |
| 78 | /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */ | |
| 79 | /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 80 | /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 81 | /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 82 | /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 83 | /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 84 | /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 85 | /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 86 | /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 87 | /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 88 | /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 89 | /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 90 | /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 91 | /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 92 | /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 93 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 94 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 95 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 96 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ | |
| 97 | }, | |
| 98 | ||
| 99 | /* Port C */ | |
| 100 | { /* conf ppar psor pdir podr pdat */ | |
| 101 | /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 102 | /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 103 | /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */ | |
| 104 | /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */ | |
| 105 | /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */ | |
| 106 | /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */ | |
| 107 | /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */ | |
| 108 | /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */ | |
| 109 | /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */ | |
| 110 | /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */ | |
| 111 | /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */ | |
| 112 | /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */ | |
| 113 | /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */ | |
| 114 | /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */ | |
| 115 | /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */ | |
| 116 | /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */ | |
| 117 | /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */ | |
| 118 | /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */ | |
| 119 | /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */ | |
| 120 | /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */ | |
| 121 | /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */ | |
| 122 | /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */ | |
| 123 | /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */ | |
| 124 | /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */ | |
| 125 | /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */ | |
| 126 | /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */ | |
| 127 | /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
| 128 | /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
| 129 | /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 130 | /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 131 | /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */ | |
| 132 | /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */ | |
| 133 | }, | |
| 134 | ||
| 135 | /* Port D */ | |
| 136 | { /* conf ppar psor pdir podr pdat */ | |
| 137 | /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */ | |
| 138 | /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */ | |
| 139 | /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */ | |
| 140 | /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 141 | /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 142 | /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 143 | /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */ | |
| 144 | /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */ | |
| 145 | /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */ | |
| 146 | /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */ | |
| 147 | /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */ | |
| 148 | /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ | |
| 149 | /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */ | |
| 150 | /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */ | |
| 151 | /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */ | |
| 152 | /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */ | |
| 153 | /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */ | |
| 154 | /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */ | |
| 155 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 156 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 157 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 158 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 159 | /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 160 | /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 161 | /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */ | |
| 162 | /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 163 | /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 164 | /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 165 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 166 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 167 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ | |
| 168 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ | |
| 169 | } | |
| 170 | }; | |
| 171 | ||
| 172 | void reset_phy (void) | |
| 173 | { | |
| 174 | volatile ioport_t *iop; | |
| c508a4ce | 175 | #if defined(CONFIG_CMD_NET) |
| ba91e26a WD |
176 | int i; |
| 177 | unsigned short val; | |
| 178 | #endif | |
| 179 | ||
| 6d0f6bcf | 180 | iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0); |
| ba91e26a WD |
181 | |
| 182 | /* Reset the PHY */ | |
| 183 | iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ | |
| c508a4ce | 184 | #if defined(CONFIG_CMD_NET) |
| ba91e26a WD |
185 | udelay(20000); |
| 186 | iop->pdat |= 0x00080000; | |
| 187 | for (i=0; i<100; i++) { | |
| 188 | udelay(20000); | |
| 48690d80 | 189 | if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) { |
| ba91e26a WD |
190 | break; |
| 191 | } | |
| 192 | } | |
| 193 | /* initialize switch */ | |
| 6d0f6bcf | 194 | m88e6060_initialize( CONFIG_SYS_PHY_ADDR ); |
| ba91e26a WD |
195 | #endif |
| 196 | } | |
| 197 | ||
| 198 | static unsigned long UPMATable[] = { | |
| 095b8a37 WD |
199 | 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ |
| 200 | 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */ | |
| 201 | 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */ | |
| 202 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */ | |
| 203 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */ | |
| 204 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ | |
| 205 | 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ | |
| 206 | 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ | |
| 207 | 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */ | |
| 208 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */ | |
| 209 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ | |
| 210 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ | |
| 211 | 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */ | |
| 212 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ | |
| 213 | 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ | |
| 214 | 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */ | |
| ba91e26a WD |
215 | }; |
| 216 | ||
| 217 | int board_early_init_f (void) | |
| 218 | { | |
| 219 | volatile immap_t *immap; | |
| 220 | volatile memctl8260_t *memctl; | |
| 221 | volatile unsigned char *dummy; | |
| 222 | int i; | |
| 223 | ||
| 6d0f6bcf | 224 | immap = (immap_t *) CONFIG_SYS_IMMR; |
| ba91e26a WD |
225 | memctl = &immap->im_memctl; |
| 226 | ||
| 227 | #if 0 | |
| 228 | /* CS2-5 - DSP via UPMA */ | |
| 229 | dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK); | |
| 230 | memctl->memc_mar = 0; | |
| 231 | memctl->memc_mamr = MxMR_OP_WARR; | |
| 232 | for (i = 0; i < 64; i++) { | |
| 233 | memctl->memc_mdr = UPMATable[i]; | |
| 234 | *dummy = 0; | |
| 235 | } | |
| 236 | memctl->memc_mamr = 0x00044440; | |
| 237 | #else | |
| 238 | /* CS7 - DPRAM via UPMA */ | |
| 239 | dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); | |
| 240 | memctl->memc_mar = 0; | |
| 241 | memctl->memc_mamr = MxMR_OP_WARR; | |
| 242 | for (i = 0; i < 64; i++) { | |
| 243 | memctl->memc_mdr = UPMATable[i]; | |
| 244 | *dummy = 0; | |
| 245 | } | |
| 246 | memctl->memc_mamr = 0x00044440; | |
| 247 | #endif | |
| 248 | return 0; | |
| 249 | } | |
| 250 | ||
| 251 | int misc_init_r (void) | |
| 252 | { | |
| 253 | volatile ioport_t *iop; | |
| 7aeda21a | 254 | __maybe_unused unsigned char temp; |
| ba91e26a WD |
255 | #if 0 |
| 256 | /* DUMP UPMA RAM */ | |
| 257 | volatile immap_t *immap; | |
| 258 | volatile memctl8260_t *memctl; | |
| 259 | volatile unsigned char *dummy; | |
| 260 | unsigned char c; | |
| 261 | int i; | |
| 262 | ||
| 6d0f6bcf | 263 | immap = (immap_t *) CONFIG_SYS_IMMR; |
| ba91e26a WD |
264 | memctl = &immap->im_memctl; |
| 265 | ||
| 266 | ||
| 267 | dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); | |
| 268 | memctl->memc_mar = 0; | |
| 269 | memctl->memc_mamr = MxMR_OP_RARR; | |
| 270 | for (i = 0; i < 64; i++) { | |
| 271 | c = *dummy; | |
| 272 | printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i, | |
| 93e14596 WD |
273 | memctl->memc_mamr, |
| 274 | memctl->memc_mar, | |
| 275 | memctl->memc_mdr ); | |
| ba91e26a WD |
276 | } |
| 277 | memctl->memc_mamr = 0x00044440; | |
| 278 | #endif | |
| 279 | /* enable buffers (DSP, DPRAM) */ | |
| 6d0f6bcf | 280 | iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0); |
| ba91e26a WD |
281 | iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ |
| 282 | ||
| 283 | /* destroy DPRAM magic */ | |
| 284 | *(volatile unsigned char *)0xf0500000 = 0x00; | |
| 285 | ||
| 286 | /* clear any pending DPRAM irq */ | |
| 287 | temp = *(volatile unsigned char *)0xf05003ff; | |
| 288 | ||
| 289 | /* write module-id into DPRAM */ | |
| 290 | *(volatile unsigned char *)0xf0500201 = 0x50; | |
| 291 | ||
| 292 | return 0; | |
| 293 | } | |
| 294 | ||
| 295 | #if defined(CONFIG_HAVE_OWN_RESET) | |
| 296 | int | |
| 882b7d72 | 297 | do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| ba91e26a WD |
298 | { |
| 299 | volatile ioport_t *iop; | |
| 300 | ||
| 6d0f6bcf | 301 | iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2); |
| ba91e26a WD |
302 | iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ |
| 303 | return 1; | |
| 304 | } | |
| 305 | #endif /* CONFIG_HAVE_OWN_RESET */ | |
| 306 | ||
| 307 | #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) | |
| 308 | ||
| 9973e3c6 | 309 | phys_size_t initdram (int board_type) |
| ba91e26a | 310 | { |
| 6d0f6bcf | 311 | #ifndef CONFIG_SYS_RAMBOOT |
| ba91e26a WD |
312 | volatile immap_t *immap; |
| 313 | volatile memctl8260_t *memctl; | |
| 314 | volatile uchar *ramaddr; | |
| 315 | int i; | |
| 316 | uchar c; | |
| 317 | ||
| 6d0f6bcf | 318 | immap = (immap_t *) CONFIG_SYS_IMMR; |
| ba91e26a | 319 | memctl = &immap->im_memctl; |
| 6d0f6bcf | 320 | ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE; |
| ba91e26a WD |
321 | c = 0xff; |
| 322 | ||
| 323 | immap->im_siu_conf.sc_ppc_acr = 0x02; | |
| 324 | immap->im_siu_conf.sc_ppc_alrh = 0x01267893; | |
| 325 | immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef; | |
| 326 | immap->im_siu_conf.sc_tescr1 = 0x00000000; | |
| 327 | immap->im_siu_conf.sc_tescr2 = 0x00000000; | |
| 328 | ||
| 6d0f6bcf JCPV |
329 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
| 330 | memctl->memc_psrt = CONFIG_SYS_PSRT; | |
| 331 | memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; | |
| 332 | memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM; | |
| ba91e26a WD |
333 | |
| 334 | /* Precharge all banks */ | |
| 6d0f6bcf | 335 | memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000; |
| ba91e26a WD |
336 | *ramaddr = c; |
| 337 | ||
| 338 | /* CBR refresh */ | |
| 6d0f6bcf | 339 | memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000; |
| ba91e26a WD |
340 | for (i = 0; i < 8; i++) |
| 341 | *ramaddr = c; | |
| 342 | ||
| 343 | /* Mode Register write */ | |
| 6d0f6bcf | 344 | memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000; |
| ba91e26a WD |
345 | *ramaddr = c; |
| 346 | ||
| 347 | /* Refresh enable */ | |
| 6d0f6bcf | 348 | memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000; |
| ba91e26a | 349 | *ramaddr = c; |
| 6d0f6bcf | 350 | #endif /* CONFIG_SYS_RAMBOOT */ |
| ba91e26a | 351 | |
| 6d0f6bcf | 352 | return (CONFIG_SYS_SDRAM_SIZE); |
| ba91e26a WD |
353 | } |
| 354 | ||
| 355 | int checkboard (void) | |
| 356 | { | |
| 357 | #ifdef CONFIG_CLKIN_66MHz | |
| 358 | puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n"); | |
| 359 | #else | |
| 360 | puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n"); | |
| 361 | #endif | |
| 362 | return 0; | |
| 363 | } |