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1 | /* |
2 | * Copyright (C) 2013 Gateworks Corporation | |
3 | * | |
4 | * Author: Tim Harvey <tharvey@gateworks.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <asm/arch/mx6-pins.h> | |
10 | #include <asm/arch/sys_proto.h> | |
11 | #include <asm/gpio.h> | |
12 | #include <asm/imx-common/mxc_i2c.h> | |
13 | #include <hwconfig.h> | |
14 | #include <power/pmic.h> | |
15 | #include <power/ltc3676_pmic.h> | |
16 | #include <power/pfuze100_pmic.h> | |
17 | ||
18 | #include "common.h" | |
19 | ||
20 | /* UART1: Function varies per baseboard */ | |
21 | static iomux_v3_cfg_t const uart1_pads[] = { | |
22 | IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
23 | IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
24 | }; | |
25 | ||
26 | /* UART2: Serial Console */ | |
27 | static iomux_v3_cfg_t const uart2_pads[] = { | |
28 | IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
29 | IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
30 | }; | |
31 | ||
32 | void setup_iomux_uart(void) | |
33 | { | |
34 | SETUP_IOMUX_PADS(uart1_pads); | |
35 | SETUP_IOMUX_PADS(uart2_pads); | |
36 | } | |
37 | ||
38 | /* I2C1: GSC */ | |
39 | static struct i2c_pads_info mx6q_i2c_pad_info0 = { | |
40 | .scl = { | |
41 | .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, | |
42 | .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, | |
43 | .gp = IMX_GPIO_NR(3, 21) | |
44 | }, | |
45 | .sda = { | |
46 | .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, | |
47 | .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, | |
48 | .gp = IMX_GPIO_NR(3, 28) | |
49 | } | |
50 | }; | |
51 | static struct i2c_pads_info mx6dl_i2c_pad_info0 = { | |
52 | .scl = { | |
53 | .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, | |
54 | .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, | |
55 | .gp = IMX_GPIO_NR(3, 21) | |
56 | }, | |
57 | .sda = { | |
58 | .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, | |
59 | .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, | |
60 | .gp = IMX_GPIO_NR(3, 28) | |
61 | } | |
62 | }; | |
63 | ||
64 | /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ | |
65 | static struct i2c_pads_info mx6q_i2c_pad_info1 = { | |
66 | .scl = { | |
67 | .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, | |
68 | .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
69 | .gp = IMX_GPIO_NR(4, 12) | |
70 | }, | |
71 | .sda = { | |
72 | .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, | |
73 | .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
74 | .gp = IMX_GPIO_NR(4, 13) | |
75 | } | |
76 | }; | |
77 | static struct i2c_pads_info mx6dl_i2c_pad_info1 = { | |
78 | .scl = { | |
79 | .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, | |
80 | .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
81 | .gp = IMX_GPIO_NR(4, 12) | |
82 | }, | |
83 | .sda = { | |
84 | .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, | |
85 | .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
86 | .gp = IMX_GPIO_NR(4, 13) | |
87 | } | |
88 | }; | |
89 | ||
90 | /* I2C3: Misc/Expansion */ | |
91 | static struct i2c_pads_info mx6q_i2c_pad_info2 = { | |
92 | .scl = { | |
93 | .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, | |
94 | .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, | |
95 | .gp = IMX_GPIO_NR(1, 3) | |
96 | }, | |
97 | .sda = { | |
98 | .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, | |
99 | .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, | |
100 | .gp = IMX_GPIO_NR(1, 6) | |
101 | } | |
102 | }; | |
103 | static struct i2c_pads_info mx6dl_i2c_pad_info2 = { | |
104 | .scl = { | |
105 | .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, | |
106 | .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, | |
107 | .gp = IMX_GPIO_NR(1, 3) | |
108 | }, | |
109 | .sda = { | |
110 | .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, | |
111 | .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, | |
112 | .gp = IMX_GPIO_NR(1, 6) | |
113 | } | |
114 | }; | |
115 | ||
116 | void setup_ventana_i2c(void) | |
117 | { | |
118 | if (is_cpu_type(MXC_CPU_MX6Q)) { | |
119 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); | |
120 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); | |
121 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); | |
122 | } else { | |
123 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); | |
124 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); | |
125 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); | |
126 | } | |
127 | } | |
128 | ||
129 | /* | |
130 | * Baseboard specific GPIO | |
131 | */ | |
132 | ||
133 | /* common to add baseboards */ | |
134 | static iomux_v3_cfg_t const gw_gpio_pads[] = { | |
135 | /* MSATA_EN */ | |
136 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
137 | /* RS232_EN# */ | |
138 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
139 | }; | |
140 | ||
141 | /* prototype */ | |
142 | static iomux_v3_cfg_t const gwproto_gpio_pads[] = { | |
143 | /* PANLEDG# */ | |
144 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
145 | /* PANLEDR# */ | |
146 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
147 | /* LOCLED# */ | |
148 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
149 | /* RS485_EN */ | |
150 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
151 | /* IOEXP_PWREN# */ | |
152 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
153 | /* IOEXP_IRQ# */ | |
154 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
155 | /* VID_EN */ | |
156 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
157 | /* DIOI2C_DIS# */ | |
158 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
159 | /* PCICK_SSON */ | |
160 | IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), | |
161 | /* PCI_RST# */ | |
162 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
163 | }; | |
164 | ||
165 | static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { | |
166 | /* PANLEDG# */ | |
167 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
168 | /* PANLEDR# */ | |
169 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
170 | /* IOEXP_PWREN# */ | |
171 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
172 | /* IOEXP_IRQ# */ | |
173 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
174 | ||
175 | /* GPS_SHDN */ | |
176 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
177 | /* VID_PWR */ | |
178 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
179 | /* PCI_RST# */ | |
180 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
181 | /* PCIESKT_WDIS# */ | |
182 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
183 | }; | |
184 | ||
185 | static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { | |
186 | /* PANLEDG# */ | |
187 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
188 | /* PANLEDR# */ | |
189 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
190 | /* IOEXP_PWREN# */ | |
191 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
192 | /* IOEXP_IRQ# */ | |
193 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
9a83a815 TH |
194 | /* CAN_STBY */ |
195 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
196 | /* MX6_LOCLED# */ |
197 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
198 | /* GPS_SHDN */ | |
199 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
200 | /* USBOTG_SEL */ | |
201 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
202 | /* VID_PWR */ | |
203 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
204 | /* PCI_RST# */ | |
205 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
206 | /* PCI_RST# (GW522x) */ | |
207 | IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), | |
9a83a815 TH |
208 | /* RS485_EN */ |
209 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
210 | /* PCIESKT_WDIS# */ |
211 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
212 | }; | |
213 | ||
214 | static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { | |
9a83a815 TH |
215 | /* CAN_STBY */ |
216 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
217 | /* USB_HUBRST# */ | |
218 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
219 | /* PANLEDG# */ |
220 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
221 | /* PANLEDR# */ | |
222 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
223 | /* MX6_LOCLED# */ | |
224 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
225 | /* IOEXP_PWREN# */ | |
226 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
227 | /* IOEXP_IRQ# */ | |
228 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
229 | /* DIOI2C_DIS# */ | |
230 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
231 | /* GPS_SHDN */ | |
232 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
233 | /* VID_EN */ | |
234 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
235 | /* PCI_RST# */ | |
236 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
9a83a815 TH |
237 | /* RS485_EN */ |
238 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
239 | /* PCIESKT_WDIS# */ |
240 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
241 | }; | |
242 | ||
243 | static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { | |
9a83a815 TH |
244 | /* CAN_STBY */ |
245 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
e56c5791 TH |
246 | /* PANLEDG# */ |
247 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
248 | /* PANLEDR# */ | |
9a83a815 | 249 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
e56c5791 TH |
250 | /* MX6_LOCLED# */ |
251 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
9a83a815 TH |
252 | /* USB_HUBRST# */ |
253 | IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), | |
e56c5791 TH |
254 | /* MIPI_DIO */ |
255 | IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), | |
256 | /* RS485_EN */ | |
257 | IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), | |
258 | /* IOEXP_PWREN# */ | |
9a83a815 | 259 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
e56c5791 | 260 | /* IOEXP_IRQ# */ |
9a83a815 | 261 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
e56c5791 TH |
262 | /* DIOI2C_DIS# */ |
263 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
264 | /* PCI_RST# */ | |
265 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
266 | /* VID_EN */ | |
267 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
9a83a815 TH |
268 | /* RS485_EN */ |
269 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
270 | /* PCIESKT_WDIS# */ |
271 | IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), | |
272 | }; | |
273 | ||
274 | static iomux_v3_cfg_t const gw551x_gpio_pads[] = { | |
9a83a815 TH |
275 | /* CAN_STBY */ |
276 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
277 | /* PANLED# */ |
278 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
279 | /* PCI_RST# */ | |
280 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
281 | /* PCIESKT_WDIS# */ | |
282 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
283 | }; | |
284 | ||
285 | static iomux_v3_cfg_t const gw552x_gpio_pads[] = { | |
9a83a815 TH |
286 | /* USBOTG_SEL */ |
287 | IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), | |
288 | /* USB_HUBRST# */ | |
289 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
290 | /* PANLEDG# */ |
291 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
292 | /* PANLEDR# */ | |
293 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
294 | /* MX6_LOCLED# */ | |
295 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
296 | /* PCI_RST# */ | |
297 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
298 | /* MX6_DIO[4:9] */ | |
299 | IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), | |
300 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
301 | IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), | |
302 | IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), | |
303 | IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), | |
304 | IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), | |
305 | /* PCIEGBE1_OFF# */ | |
306 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), | |
307 | /* PCIEGBE2_OFF# */ | |
308 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
309 | /* PCIESKT_WDIS# */ | |
310 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
311 | }; | |
312 | ||
313 | ||
314 | /* | |
315 | * Board Specific GPIO | |
316 | */ | |
317 | struct ventana gpio_cfg[GW_UNKNOWN] = { | |
318 | /* GW5400proto */ | |
319 | { | |
320 | .gpio_pads = gw54xx_gpio_pads, | |
321 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
322 | .dio_cfg = { | |
323 | { | |
324 | { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, | |
325 | IMX_GPIO_NR(1, 9), | |
326 | { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, | |
327 | 1 | |
328 | }, | |
329 | { | |
330 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
331 | IMX_GPIO_NR(1, 19), | |
332 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
333 | 2 | |
334 | }, | |
335 | { | |
336 | { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, | |
337 | IMX_GPIO_NR(2, 9), | |
338 | { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, | |
339 | 3 | |
340 | }, | |
341 | { | |
342 | { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, | |
343 | IMX_GPIO_NR(2, 10), | |
344 | { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, | |
345 | 4 | |
346 | }, | |
347 | }, | |
348 | .num_gpios = 4, | |
349 | .leds = { | |
350 | IMX_GPIO_NR(4, 6), | |
351 | IMX_GPIO_NR(4, 10), | |
352 | IMX_GPIO_NR(4, 15), | |
353 | }, | |
354 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
355 | .mezz_pwren = IMX_GPIO_NR(4, 7), | |
356 | .mezz_irq = IMX_GPIO_NR(4, 9), | |
357 | .rs485en = IMX_GPIO_NR(3, 24), | |
358 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
359 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
360 | }, | |
361 | ||
362 | /* GW51xx */ | |
363 | { | |
364 | .gpio_pads = gw51xx_gpio_pads, | |
365 | .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, | |
366 | .dio_cfg = { | |
367 | { | |
368 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
369 | IMX_GPIO_NR(1, 16), | |
370 | { 0, 0 }, | |
371 | 0 | |
372 | }, | |
373 | { | |
374 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
375 | IMX_GPIO_NR(1, 19), | |
376 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
377 | 2 | |
378 | }, | |
379 | { | |
380 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
381 | IMX_GPIO_NR(1, 17), | |
382 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
383 | 3 | |
384 | }, | |
385 | { | |
386 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
387 | IMX_GPIO_NR(1, 18), | |
388 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
389 | 4 | |
390 | }, | |
391 | }, | |
392 | .num_gpios = 4, | |
393 | .leds = { | |
394 | IMX_GPIO_NR(4, 6), | |
395 | IMX_GPIO_NR(4, 10), | |
396 | }, | |
397 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
398 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
399 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
400 | .gps_shdn = IMX_GPIO_NR(1, 2), | |
401 | .vidin_en = IMX_GPIO_NR(5, 20), | |
402 | .wdis = IMX_GPIO_NR(7, 12), | |
403 | }, | |
404 | ||
405 | /* GW52xx */ | |
406 | { | |
407 | .gpio_pads = gw52xx_gpio_pads, | |
408 | .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, | |
409 | .dio_cfg = { | |
410 | { | |
411 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
412 | IMX_GPIO_NR(1, 16), | |
413 | { 0, 0 }, | |
414 | 0 | |
415 | }, | |
416 | { | |
417 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
418 | IMX_GPIO_NR(1, 19), | |
419 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
420 | 2 | |
421 | }, | |
422 | { | |
423 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
424 | IMX_GPIO_NR(1, 17), | |
425 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
426 | 3 | |
427 | }, | |
428 | { | |
429 | { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
430 | IMX_GPIO_NR(1, 20), | |
431 | { 0, 0 }, | |
432 | 0 | |
433 | }, | |
434 | }, | |
435 | .num_gpios = 4, | |
436 | .leds = { | |
437 | IMX_GPIO_NR(4, 6), | |
438 | IMX_GPIO_NR(4, 7), | |
439 | IMX_GPIO_NR(4, 15), | |
440 | }, | |
441 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
442 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
443 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
444 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
445 | .vidin_en = IMX_GPIO_NR(3, 31), | |
446 | .usb_sel = IMX_GPIO_NR(1, 2), | |
447 | .wdis = IMX_GPIO_NR(7, 12), | |
448 | }, | |
449 | ||
450 | /* GW53xx */ | |
451 | { | |
452 | .gpio_pads = gw53xx_gpio_pads, | |
453 | .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, | |
454 | .dio_cfg = { | |
455 | { | |
456 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
457 | IMX_GPIO_NR(1, 16), | |
458 | { 0, 0 }, | |
459 | 0 | |
460 | }, | |
461 | { | |
462 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
463 | IMX_GPIO_NR(1, 19), | |
464 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
465 | 2 | |
466 | }, | |
467 | { | |
468 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
469 | IMX_GPIO_NR(1, 17), | |
470 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
471 | 3 | |
472 | }, | |
473 | { | |
474 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
475 | IMX_GPIO_NR(1, 20), | |
476 | { 0, 0 }, | |
477 | 0 | |
478 | }, | |
479 | }, | |
480 | .num_gpios = 4, | |
481 | .leds = { | |
482 | IMX_GPIO_NR(4, 6), | |
483 | IMX_GPIO_NR(4, 7), | |
484 | IMX_GPIO_NR(4, 15), | |
485 | }, | |
486 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
487 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
488 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
489 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
490 | .vidin_en = IMX_GPIO_NR(3, 31), | |
491 | .wdis = IMX_GPIO_NR(7, 12), | |
492 | }, | |
493 | ||
494 | /* GW54xx */ | |
495 | { | |
496 | .gpio_pads = gw54xx_gpio_pads, | |
497 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
498 | .dio_cfg = { | |
499 | { | |
500 | { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, | |
501 | IMX_GPIO_NR(1, 9), | |
502 | { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, | |
503 | 1 | |
504 | }, | |
505 | { | |
506 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
507 | IMX_GPIO_NR(1, 19), | |
508 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
509 | 2 | |
510 | }, | |
511 | { | |
512 | { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, | |
513 | IMX_GPIO_NR(2, 9), | |
514 | { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, | |
515 | 3 | |
516 | }, | |
517 | { | |
518 | { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, | |
519 | IMX_GPIO_NR(2, 10), | |
520 | { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, | |
521 | 4 | |
522 | }, | |
523 | }, | |
524 | .num_gpios = 4, | |
525 | .leds = { | |
526 | IMX_GPIO_NR(4, 6), | |
527 | IMX_GPIO_NR(4, 7), | |
528 | IMX_GPIO_NR(4, 15), | |
529 | }, | |
530 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
531 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
532 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
533 | .rs485en = IMX_GPIO_NR(7, 1), | |
534 | .vidin_en = IMX_GPIO_NR(3, 31), | |
535 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
536 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
537 | .wdis = IMX_GPIO_NR(5, 17), | |
538 | }, | |
539 | ||
540 | /* GW551x */ | |
541 | { | |
542 | .gpio_pads = gw551x_gpio_pads, | |
543 | .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, | |
544 | .dio_cfg = { | |
e56c5791 TH |
545 | { |
546 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
547 | IMX_GPIO_NR(1, 19), | |
548 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
549 | 2 | |
550 | }, | |
551 | { | |
552 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
553 | IMX_GPIO_NR(1, 17), | |
554 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
555 | 3 | |
556 | }, | |
e56c5791 TH |
557 | }, |
558 | .num_gpios = 2, | |
559 | .leds = { | |
560 | IMX_GPIO_NR(4, 7), | |
561 | }, | |
562 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
563 | .wdis = IMX_GPIO_NR(7, 12), | |
564 | }, | |
565 | ||
566 | /* GW552x */ | |
567 | { | |
568 | .gpio_pads = gw552x_gpio_pads, | |
569 | .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, | |
570 | .dio_cfg = { | |
9a83a815 TH |
571 | { |
572 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
573 | IMX_GPIO_NR(1, 16), | |
574 | { 0, 0 }, | |
575 | 0 | |
576 | }, | |
e56c5791 TH |
577 | { |
578 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
579 | IMX_GPIO_NR(1, 19), | |
580 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
581 | 2 | |
582 | }, | |
583 | { | |
584 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
585 | IMX_GPIO_NR(1, 17), | |
586 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
587 | 3 | |
588 | }, | |
9a83a815 TH |
589 | { |
590 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
591 | IMX_GPIO_NR(1, 20), | |
592 | { 0, 0 }, | |
593 | 0 | |
594 | }, | |
e56c5791 TH |
595 | }, |
596 | .num_gpios = 4, | |
597 | .leds = { | |
598 | IMX_GPIO_NR(4, 6), | |
599 | IMX_GPIO_NR(4, 7), | |
600 | IMX_GPIO_NR(4, 15), | |
601 | }, | |
602 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
9a83a815 | 603 | .usb_sel = IMX_GPIO_NR(1, 7), |
e56c5791 TH |
604 | .wdis = IMX_GPIO_NR(7, 12), |
605 | }, | |
606 | }; | |
607 | ||
608 | void setup_iomux_gpio(int board, struct ventana_board_info *info) | |
609 | { | |
610 | int i; | |
611 | ||
612 | /* iomux common to all Ventana boards */ | |
613 | SETUP_IOMUX_PADS(gw_gpio_pads); | |
614 | ||
615 | /* OTG power off */ | |
616 | gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); | |
617 | gpio_direction_output(GP_USB_OTG_PWR, 0); | |
618 | ||
619 | /* MSATA Enable - default to PCI */ | |
620 | gpio_request(GP_MSATA_SEL, "msata_en"); | |
621 | gpio_direction_output(GP_MSATA_SEL, 0); | |
622 | ||
623 | /* RS232_EN# */ | |
624 | gpio_request(GP_RS232_EN, "rs232_en"); | |
625 | gpio_direction_output(GP_RS232_EN, 0); | |
626 | ||
627 | if (board >= GW_UNKNOWN) | |
628 | return; | |
629 | ||
630 | /* board specific iomux */ | |
631 | imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, | |
632 | gpio_cfg[board].num_pads); | |
633 | ||
634 | /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ | |
635 | if (board == GW52xx && info->model[4] == '2') | |
636 | gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); | |
637 | ||
638 | /* assert PCI_RST# */ | |
639 | gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); | |
640 | gpio_direction_output(gpio_cfg[board].pcie_rst, 0); | |
641 | ||
642 | /* turn off (active-high) user LED's */ | |
643 | for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { | |
644 | char name[16]; | |
645 | if (gpio_cfg[board].leds[i]) { | |
646 | sprintf(name, "led_user%d", i); | |
647 | gpio_request(gpio_cfg[board].leds[i], name); | |
648 | gpio_direction_output(gpio_cfg[board].leds[i], 1); | |
649 | } | |
650 | } | |
651 | ||
652 | /* Expansion Mezzanine IO */ | |
653 | if (gpio_cfg[board].mezz_pwren) { | |
654 | gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); | |
655 | gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); | |
656 | } | |
657 | if (gpio_cfg[board].mezz_irq) { | |
658 | gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); | |
659 | gpio_direction_input(gpio_cfg[board].mezz_irq); | |
660 | } | |
661 | ||
662 | /* RS485 Transmit Enable */ | |
663 | if (gpio_cfg[board].rs485en) { | |
664 | gpio_request(gpio_cfg[board].rs485en, "rs485_en"); | |
665 | gpio_direction_output(gpio_cfg[board].rs485en, 0); | |
666 | } | |
667 | ||
668 | /* GPS_SHDN */ | |
669 | if (gpio_cfg[board].gps_shdn) { | |
670 | gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); | |
671 | gpio_direction_output(gpio_cfg[board].gps_shdn, 1); | |
672 | } | |
673 | ||
674 | /* Analog video codec power enable */ | |
675 | if (gpio_cfg[board].vidin_en) { | |
676 | gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); | |
677 | gpio_direction_output(gpio_cfg[board].vidin_en, 1); | |
678 | } | |
679 | ||
680 | /* DIOI2C_DIS# */ | |
681 | if (gpio_cfg[board].dioi2c_en) { | |
682 | gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); | |
683 | gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); | |
684 | } | |
685 | ||
686 | /* PCICK_SSON: disable spread-spectrum clock */ | |
687 | if (gpio_cfg[board].pcie_sson) { | |
688 | gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); | |
689 | gpio_direction_output(gpio_cfg[board].pcie_sson, 0); | |
690 | } | |
691 | ||
692 | /* USBOTG mux routing */ | |
693 | if (gpio_cfg[board].usb_sel) { | |
694 | gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); | |
695 | gpio_direction_output(gpio_cfg[board].usb_sel, 0); | |
696 | } | |
697 | ||
698 | /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ | |
699 | if (gpio_cfg[board].wdis) { | |
700 | gpio_request(gpio_cfg[board].wdis, "wlan_dis"); | |
701 | gpio_direction_output(gpio_cfg[board].wdis, 1); | |
702 | } | |
703 | } | |
704 | ||
705 | /* setup GPIO pinmux and default configuration per baseboard and env */ | |
706 | void setup_board_gpio(int board, struct ventana_board_info *info) | |
707 | { | |
708 | const char *s; | |
709 | char arg[10]; | |
710 | size_t len; | |
711 | int i; | |
712 | int quiet = simple_strtol(getenv("quiet"), NULL, 10); | |
713 | ||
714 | if (board >= GW_UNKNOWN) | |
715 | return; | |
716 | ||
717 | /* RS232_EN# */ | |
718 | gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); | |
719 | ||
720 | /* MSATA Enable */ | |
721 | if (is_cpu_type(MXC_CPU_MX6Q) && | |
722 | test_bit(EECONFIG_SATA, info->config)) { | |
723 | gpio_direction_output(GP_MSATA_SEL, | |
724 | (hwconfig("msata")) ? 1 : 0); | |
725 | } | |
726 | ||
727 | /* USBOTG Select (PCISKT or FrontPanel) */ | |
728 | if (gpio_cfg[board].usb_sel) { | |
729 | gpio_direction_output(gpio_cfg[board].usb_sel, | |
730 | (hwconfig("usb_pcisel")) ? 1 : 0); | |
731 | } | |
732 | ||
733 | /* | |
734 | * Configure DIO pinmux/padctl registers | |
735 | * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions | |
736 | */ | |
9a83a815 | 737 | for (i = 0; i < gpio_cfg[board].num_gpios; i++) { |
e56c5791 TH |
738 | struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; |
739 | iomux_v3_cfg_t ctrl = DIO_PAD_CFG; | |
740 | unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; | |
741 | ||
742 | if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) | |
743 | continue; | |
744 | sprintf(arg, "dio%d", i); | |
745 | if (!hwconfig(arg)) | |
746 | continue; | |
747 | s = hwconfig_subarg(arg, "padctrl", &len); | |
748 | if (s) { | |
749 | ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) | |
750 | & 0x1ffff) | MUX_MODE_SION; | |
751 | } | |
752 | if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { | |
753 | if (!quiet) { | |
754 | printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, | |
755 | (cfg->gpio_param/32)+1, | |
756 | cfg->gpio_param%32, | |
757 | cfg->gpio_param); | |
758 | } | |
759 | imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | | |
760 | ctrl); | |
761 | gpio_requestf(cfg->gpio_param, "dio%d", i); | |
762 | gpio_direction_input(cfg->gpio_param); | |
763 | } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && | |
764 | cfg->pwm_padmux) { | |
765 | if (!quiet) | |
766 | printf("DIO%d: pwm%d\n", i, cfg->pwm_param); | |
767 | imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | | |
768 | MUX_PAD_CTRL(ctrl)); | |
769 | } | |
770 | } | |
771 | ||
772 | if (!quiet) { | |
773 | if (is_cpu_type(MXC_CPU_MX6Q) && | |
774 | (test_bit(EECONFIG_SATA, info->config))) { | |
775 | printf("MSATA: %s\n", (hwconfig("msata") ? | |
776 | "enabled" : "disabled")); | |
777 | } | |
778 | printf("RS232: %s\n", (hwconfig("rs232")) ? | |
779 | "enabled" : "disabled"); | |
780 | } | |
781 | } | |
782 | ||
783 | /* setup board specific PMIC */ | |
6d38f3a8 | 784 | void setup_pmic(void) |
e56c5791 TH |
785 | { |
786 | struct pmic *p; | |
787 | u32 reg; | |
788 | ||
6d38f3a8 TH |
789 | i2c_set_bus_num(CONFIG_I2C_PMIC); |
790 | ||
e56c5791 | 791 | /* configure PFUZE100 PMIC */ |
6d38f3a8 TH |
792 | if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { |
793 | debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); | |
e56c5791 TH |
794 | power_pfuze100_init(CONFIG_I2C_PMIC); |
795 | p = pmic_get("PFUZE100"); | |
796 | if (p && !pmic_probe(p)) { | |
797 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); | |
798 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); | |
799 | ||
800 | /* Set VGEN1 to 1.5V and enable */ | |
801 | pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); | |
802 | reg &= ~(LDO_VOL_MASK); | |
803 | reg |= (LDOA_1_50V | LDO_EN); | |
804 | pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); | |
805 | ||
806 | /* Set SWBST to 5.0V and enable */ | |
807 | pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); | |
808 | reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); | |
809 | reg |= (SWBST_5_00V | SWBST_MODE_AUTO); | |
810 | pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); | |
811 | } | |
812 | } | |
813 | ||
814 | /* configure LTC3676 PMIC */ | |
6d38f3a8 TH |
815 | else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { |
816 | debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); | |
e56c5791 TH |
817 | power_ltc3676_init(CONFIG_I2C_PMIC); |
818 | p = pmic_get("LTC3676_PMIC"); | |
819 | if (p && !pmic_probe(p)) { | |
820 | puts("PMIC: LTC3676\n"); | |
821 | /* | |
822 | * set board-specific scalar for max CPU frequency | |
823 | * per CPU based on the LDO enabled Operating Ranges | |
824 | * defined in the respective IMX6DQ and IMX6SDL | |
825 | * datasheets. The voltage resulting from the R1/R2 | |
826 | * feedback inputs on Ventana is 1308mV. Note that this | |
827 | * is a bit shy of the Vmin of 1350mV in the datasheet | |
828 | * for LDO enabled mode but is as high as we can go. | |
829 | * | |
830 | * We will rely on an OS kernel driver to properly | |
831 | * regulate these per CPU operating point and use LDO | |
832 | * bypass mode when using the higher frequency | |
833 | * operating points to compensate as LDO bypass mode | |
834 | * allows the rails be 125mV lower. | |
835 | */ | |
836 | /* mask PGOOD during SW1 transition */ | |
837 | pmic_reg_write(p, LTC3676_DVB1B, | |
838 | 0x1f | LTC3676_PGOOD_MASK); | |
839 | /* set SW1 (VDD_SOC) */ | |
840 | pmic_reg_write(p, LTC3676_DVB1A, 0x1f); | |
841 | ||
842 | /* mask PGOOD during SW3 transition */ | |
843 | pmic_reg_write(p, LTC3676_DVB3B, | |
844 | 0x1f | LTC3676_PGOOD_MASK); | |
845 | /* set SW3 (VDD_ARM) */ | |
846 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
847 | } | |
848 | } | |
849 | } |