[people/ms/u-boot.git] / board / gateworks / gw_ventana / gsc.c

/*
 * Copyright (C) 2013 Gateworks Corporation
 *
 * Author: Tim Harvey <tharvey@gateworks.com>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <asm/errno.h>
#include <common.h>
#include <i2c.h>
#include <linux/ctype.h>

#include "gsc.h"

#define MINMAX(n, percent)	((n)*(100-percent)/100), ((n)*(100+percent)/100)

/*
 * The Gateworks System Controller will fail to ACK a master transaction if
 * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
 * When this does occur, it will never be busy long enough to fail more than
 * 2 back-to-back transfers.  Thus we wrap i2c_read and i2c_write with
 * 3 retries.
 */
int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
	int retry = 3;
	int n = 0;
	int ret;

	while (n++ < retry) {
		ret = i2c_read(chip, addr, alen, buf, len);
		if (!ret)
			break;
		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
		      n, ret);
		if (ret != -ENODEV)
			break;
		mdelay(10);
	}
	return ret;
}

int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
	int retry = 3;
	int n = 0;
	int ret;

	while (n++ < retry) {
		ret = i2c_write(chip, addr, alen, buf, len);
		if (!ret)
			break;
		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
		      n, ret);
		if (ret != -ENODEV)
			break;
		mdelay(10);
	}
	mdelay(100);
	return ret;
}

#ifdef CONFIG_CMD_GSC
static void read_hwmon(const char *name, uint reg, uint size, uint low,
		       uint high)
{
	unsigned char buf[3];
	uint ui;

	printf("%-8s:", name);
	memset(buf, 0, sizeof(buf));
	if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
		puts("fRD\n");
	} else {
		ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
		if (ui == 0xffffff)
			printf("invalid");
		else if (ui < low)
			printf("%d Failed - Low", ui);
		else if (ui > high)
			printf("%d Failed - High", ui);
		else
			printf("%d", ui);
	}
	puts("\n");
}

int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	const char *model = getenv("model");

	i2c_set_bus_num(0);
	read_hwmon("Temp",     GSC_HWMON_TEMP, 2, 0, 9000);
	read_hwmon("VIN",      GSC_HWMON_VIN, 3, 8000, 60000);
	read_hwmon("VBATT",    GSC_HWMON_VBATT, 3, 1800, 3500);
	read_hwmon("VDD_3P3",  GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
	read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
	read_hwmon("VDD_DDR",  GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
	read_hwmon("VDD_5P0",  GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
	read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
	read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));

	switch (model[3]) {
	case '1': /* GW51xx */
		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
		break;
	case '2': /* GW52xx */
	case '3': /* GW53xx */
		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
		read_hwmon("VDD_1P0",  GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
		break;
	case '4': /* GW54xx */
		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
		read_hwmon("VDD_1P0",  GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
		break;
	case '5': /* GW55xx */
		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
		break;
	}
	return 0;
}

U_BOOT_CMD(gsc, 1, 1, do_gsc,
	   "GSC test",
	   ""
);

#endif /* CONFIG_CMD_GSC */
Commit	Line	Data
59189a8b TH	1	/*
	2	* Copyright (C) 2013 Gateworks Corporation
	3	*
	4	* Author: Tim Harvey <tharvey@gateworks.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <asm/errno.h>
	10	#include <common.h>
	11	#include <i2c.h>
	12	#include <linux/ctype.h>
	13
	14	#include "gsc.h"
	15
	16	#define MINMAX(n, percent) ((n)(100-percent)/100), ((n)(100+percent)/100)
	17
	18	/*
	19	* The Gateworks System Controller will fail to ACK a master transaction if
	20	* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
	21	* When this does occur, it will never be busy long enough to fail more than
	22	* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
	23	* 3 retries.
	24	*/
	25	int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
	26	{
	27	int retry = 3;
	28	int n = 0;
	29	int ret;
	30
	31	while (n++ < retry) {
	32	ret = i2c_read(chip, addr, alen, buf, len);
	33	if (!ret)
	34	break;
	35	debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
	36	n, ret);
	37	if (ret != -ENODEV)
	38	break;
	39	mdelay(10);
	40	}
	41	return ret;
	42	}
	43
	44	int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
	45	{
	46	int retry = 3;
	47	int n = 0;
	48	int ret;
	49
	50	while (n++ < retry) {
	51	ret = i2c_write(chip, addr, alen, buf, len);
	52	if (!ret)
	53	break;
	54	debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
	55	n, ret);
	56	if (ret != -ENODEV)
	57	break;
	58	mdelay(10);
	59	}
e5131d53	60	mdelay(100);
59189a8b TH	61	return ret;
	62	}
	63
	64	#ifdef CONFIG_CMD_GSC
	65	static void read_hwmon(const char *name, uint reg, uint size, uint low,
	66	uint high)
	67	{
	68	unsigned char buf[3];
	69	uint ui;
	70
	71	printf("%-8s:", name);
	72	memset(buf, 0, sizeof(buf));
	73	if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
	74	puts("fRD\n");
	75	} else {
	76	ui = buf[0] \| (buf[1]<<8) \| (buf[2]<<16);
	77	if (ui == 0xffffff)
	78	printf("invalid");
	79	else if (ui < low)
	80	printf("%d Failed - Low", ui);
	81	else if (ui > high)
	82	printf("%d Failed - High", ui);
	83	else
	84	printf("%d", ui);
	85	}
	86	puts("\n");
	87	}
	88
	89	int do_gsc(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	90	{
	91	const char *model = getenv("model");
	92
	93	i2c_set_bus_num(0);
	94	read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000);
	95	read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000);
	96	read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500);
	97	read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
	98	read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
	99	read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
	100	read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
	101	read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
	102	read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));
	103
	104	switch (model[3]) {
	105	case '1': /* GW51xx */
	106	read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
	107	read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
	108	break;
	109	case '2': /* GW52xx */
	110	case '3': /* GW53xx */
	111	read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
	112	read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
	113	read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
	114	break;
	115	case '4': /* GW54xx */
	116	read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
	117	read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
	118	read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
	119	break;
3aa22674 TH	120	case '5': /* GW55xx */
	121	read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
	122	read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
	123	break;
59189a8b TH	124	}
	125	return 0;
	126	}
	127
	128	U_BOOT_CMD(gsc, 1, 1, do_gsc,
	129	"GSC test",
	130	""
	131	);
	132
	133	#endif /* CONFIG_CMD_GSC */