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gw_ventana: Use the generic spl_sd.cfg
[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana.c
CommitLineData
59189a8b
TH		 1/*
2 * Copyright (C) 2013 Gateworks Corporation
3 *
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
14#include <asm/arch/mx6-pins.h>
7a278f9f 15#include <asm/arch/mxc_hdmi.h>
59189a8b
TH		 16#include <asm/arch/crm_regs.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/gpio.h>
19#include <asm/imx-common/iomux-v3.h>
20#include <asm/imx-common/mxc_i2c.h>
21#include <asm/imx-common/boot_mode.h>
22#include <asm/imx-common/sata.h>
3acb011c 23#include <asm/imx-common/spi.h>
7a278f9f 24#include <asm/imx-common/video.h>
59189a8b
TH		 25#include <jffs2/load_kernel.h>
26#include <hwconfig.h>
27#include <i2c.h>
28#include <linux/ctype.h>
29#include <fdt_support.h>
30#include <fsl_esdhc.h>
31#include <miiphy.h>
32#include <mmc.h>
33#include <mtd_node.h>
34#include <netdev.h>
dad08286 35#include <pci.h>
59189a8b 36#include <power/pmic.h>
234d89da 37#include <power/ltc3676_pmic.h>
59189a8b 38#include <power/pfuze100_pmic.h>
59189a8b
TH		 39#include <fdt_support.h>
40#include <jffs2/load_kernel.h>
41#include <spi_flash.h>
42
43#include "gsc.h"
44#include "ventana_eeprom.h"
45
46DECLARE_GLOBAL_DATA_PTR;
47
48/* GPIO's common to all baseboards */
49#define GP_PHY_RST IMX_GPIO_NR(1, 30)
50#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
51#define GP_SD3_CD IMX_GPIO_NR(7, 0)
52#define GP_RS232_EN IMX_GPIO_NR(2, 11)
53#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
54
59189a8b
TH		 55#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58
59#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
61 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
62
63#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
65 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
66
67#define SPI_PAD_CTRL (PAD_CTL_HYS | \
68 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70
71#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
72 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
73 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
74
75#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
76 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
77 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
78
d9d41492
TH		 79#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
80 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
81 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
82
83#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
84
85
59189a8b
TH		 86/*
87 * EEPROM board info struct populated by read_eeprom so that we only have to
88 * read it once.
89 */
9c0fe83e 90struct ventana_board_info ventana_info;
59189a8b 91
59189a8b
TH		 92int board_type;
93
94/* UART1: Function varies per baseboard */
95iomux_v3_cfg_t const uart1_pads[] = {
680e8db4
TH		 96 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
59189a8b
TH		 98};
99
100/* UART2: Serial Console */
101iomux_v3_cfg_t const uart2_pads[] = {
680e8db4
TH		 102 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
103 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
59189a8b
TH		 104};
105
106#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
107
108/* I2C1: GSC */
680e8db4 109struct i2c_pads_info mx6q_i2c_pad_info0 = {
59189a8b 110 .scl = {
680e8db4
TH		 111 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
112 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
59189a8b
TH		 113 .gp = IMX_GPIO_NR(3, 21)
114 },
115 .sda = {
680e8db4
TH		 116 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
117 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
118 .gp = IMX_GPIO_NR(3, 28)
119 }
120};
121struct i2c_pads_info mx6dl_i2c_pad_info0 = {
122 .scl = {
123 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
124 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
125 .gp = IMX_GPIO_NR(3, 21)
126 },
127 .sda = {
128 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
129 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
59189a8b
TH		 130 .gp = IMX_GPIO_NR(3, 28)
131 }
132};
133
134/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
680e8db4 135struct i2c_pads_info mx6q_i2c_pad_info1 = {
59189a8b 136 .scl = {
680e8db4
TH		 137 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
138 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
59189a8b
TH		 139 .gp = IMX_GPIO_NR(4, 12)
140 },
141 .sda = {
680e8db4
TH		 142 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
143 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
144 .gp = IMX_GPIO_NR(4, 13)
145 }
146};
147struct i2c_pads_info mx6dl_i2c_pad_info1 = {
148 .scl = {
149 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
150 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
151 .gp = IMX_GPIO_NR(4, 12)
152 },
153 .sda = {
154 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
155 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
59189a8b
TH		 156 .gp = IMX_GPIO_NR(4, 13)
157 }
158};
159
160/* I2C3: Misc/Expansion */
680e8db4
TH		 161struct i2c_pads_info mx6q_i2c_pad_info2 = {
162 .scl = {
163 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
164 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
165 .gp = IMX_GPIO_NR(1, 3)
166 },
167 .sda = {
168 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
169 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
170 .gp = IMX_GPIO_NR(1, 6)
171 }
172};
173struct i2c_pads_info mx6dl_i2c_pad_info2 = {
59189a8b 174 .scl = {
680e8db4
TH		 175 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
176 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
59189a8b
TH		 177 .gp = IMX_GPIO_NR(1, 3)
178 },
179 .sda = {
680e8db4
TH		 180 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
181 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
59189a8b
TH		 182 .gp = IMX_GPIO_NR(1, 6)
183 }
184};
185
186/* MMC */
187iomux_v3_cfg_t const usdhc3_pads[] = {
680e8db4
TH		 188 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
189 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
190 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
191 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
192 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
193 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
194 /* CD */
d9d41492 195 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
59189a8b
TH		 196};
197
198/* ENET */
199iomux_v3_cfg_t const enet_pads[] = {
680e8db4
TH		 200 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
201 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
202 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
203 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
204 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
205 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
206 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
207 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
208 MUX_PAD_CTRL(ENET_PAD_CTRL)),
209 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
210 MUX_PAD_CTRL(ENET_PAD_CTRL)),
211 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
212 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
213 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
214 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
215 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
216 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
217 MUX_PAD_CTRL(ENET_PAD_CTRL)),
59189a8b 218 /* PHY nRST */
d9d41492 219 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
59189a8b
TH		 220};
221
222/* NAND */
223iomux_v3_cfg_t const nfc_pads[] = {
680e8db4
TH		 224 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
225 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
226 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
227 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
228 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
229 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
230 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
231 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
232 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
233 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
234 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
235 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
236 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
237 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
238 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
59189a8b
TH		 239};
240
241#ifdef CONFIG_CMD_NAND
242static void setup_gpmi_nand(void)
243{
244 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
245
246 /* config gpmi nand iomux */
680e8db4 247 SETUP_IOMUX_PADS(nfc_pads);
59189a8b
TH		 248
249 /* config gpmi and bch clock to 100 MHz */
250 clrsetbits_le32(&mxc_ccm->cs2cdr,
251 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
252 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
253 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
254 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
255 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
256 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
257
258 /* enable gpmi and bch clock gating */
259 setbits_le32(&mxc_ccm->CCGR4,
260 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
261 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
262 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
263 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
264 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
265
266 /* enable apbh clock gating */
267 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
268}
269#endif
270
271static void setup_iomux_enet(void)
272{
680e8db4 273 SETUP_IOMUX_PADS(enet_pads);
59189a8b
TH		 274
275 /* toggle PHY_RST# */
276 gpio_direction_output(GP_PHY_RST, 0);
277 mdelay(2);
278 gpio_set_value(GP_PHY_RST, 1);
279}
280
281static void setup_iomux_uart(void)
282{
680e8db4
TH		 283 SETUP_IOMUX_PADS(uart1_pads);
284 SETUP_IOMUX_PADS(uart2_pads);
59189a8b
TH		 285}
286
287#ifdef CONFIG_USB_EHCI_MX6
288iomux_v3_cfg_t const usb_pads[] = {
d9d41492
TH		 289 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
290 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
680e8db4 291 /* OTG PWR */
d9d41492 292 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
59189a8b
TH		 293};
294
295int board_ehci_hcd_init(int port)
296{
297 struct ventana_board_info *info = &ventana_info;
298
680e8db4 299 SETUP_IOMUX_PADS(usb_pads);
59189a8b
TH		 300
301 /* Reset USB HUB (present on GW54xx/GW53xx) */
302 switch (info->model[3]) {
303 case '3': /* GW53xx */
3aa22674 304 case '5': /* GW552x */
d9d41492 305 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
59189a8b
TH		 306 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
307 mdelay(2);
308 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
309 break;
310 case '4': /* GW54xx */
d9d41492 311 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
59189a8b
TH		 312 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
313 mdelay(2);
314 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
315 break;
316 }
317
318 return 0;
319}
320
321int board_ehci_power(int port, int on)
322{
323 if (port)
324 return 0;
325 gpio_set_value(GP_USB_OTG_PWR, on);
326 return 0;
327}
328#endif /* CONFIG_USB_EHCI_MX6 */
329
330#ifdef CONFIG_FSL_ESDHC
331struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
332
333int board_mmc_getcd(struct mmc *mmc)
334{
335 /* Card Detect */
336 gpio_direction_input(GP_SD3_CD);
337 return !gpio_get_value(GP_SD3_CD);
338}
339
340int board_mmc_init(bd_t *bis)
341{
342 /* Only one USDHC controller on Ventana */
680e8db4 343 SETUP_IOMUX_PADS(usdhc3_pads);
59189a8b
TH		 344 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
345 usdhc_cfg.max_bus_width = 4;
346
347 return fsl_esdhc_initialize(bis, &usdhc_cfg);
348}
349#endif /* CONFIG_FSL_ESDHC */
350
351#ifdef CONFIG_MXC_SPI
352iomux_v3_cfg_t const ecspi1_pads[] = {
353 /* SS1 */
680e8db4
TH		 354 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
355 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
356 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
357 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
59189a8b
TH		 358};
359
155fa9af
NK		 360int board_spi_cs_gpio(unsigned bus, unsigned cs)
361{
362 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
363}
364
59189a8b
TH		 365static void setup_spi(void)
366{
155fa9af 367 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
680e8db4 368 SETUP_IOMUX_PADS(ecspi1_pads);
59189a8b
TH		 369}
370#endif
371
372/* configure eth0 PHY board-specific LED behavior */
373int board_phy_config(struct phy_device *phydev)
374{
375 unsigned short val;
376
377 /* Marvel 88E1510 */
378 if (phydev->phy_id == 0x1410dd1) {
379 /*
380 * Page 3, Register 16: LED[2:0] Function Control Register
381 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
382 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
383 */
384 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
385 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
386 val &= 0xff00;
387 val |= 0x0017;
388 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
389 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
390 }
391
392 if (phydev->drv->config)
393 phydev->drv->config(phydev);
394
395 return 0;
396}
397
398int board_eth_init(bd_t *bis)
399{
400 setup_iomux_enet();
401
402#ifdef CONFIG_FEC_MXC
3aa22674
TH		 403 if (board_type != GW552x)
404 cpu_eth_init(bis);
59189a8b
TH		 405#endif
406
407#ifdef CONFIG_CI_UDC
408 /* For otg ethernet*/
409 usb_eth_initialize(bis);
410#endif
411
412 return 0;
413}
414
7a278f9f
TH		 415#if defined(CONFIG_VIDEO_IPUV3)
416
417static void enable_hdmi(struct display_info_t const *dev)
418{
419 imx_enable_hdmi_phy();
420}
421
422static int detect_i2c(struct display_info_t const *dev)
423{
424 return i2c_set_bus_num(dev->bus) == 0 &&
425 i2c_probe(dev->addr) == 0;
426}
427
428static void enable_lvds(struct display_info_t const *dev)
429{
430 struct iomuxc *iomux = (struct iomuxc *)
431 IOMUXC_BASE_ADDR;
432
433 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
434 u32 reg = readl(&iomux->gpr[2]);
435 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
436 writel(reg, &iomux->gpr[2]);
437
438 /* Enable Backlight */
d9d41492 439 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
7a278f9f
TH		 440 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
441}
442
443struct display_info_t const displays[] = {{
444 /* HDMI Output */
445 .bus = -1,
446 .addr = 0,
447 .pixfmt = IPU_PIX_FMT_RGB24,
448 .detect = detect_hdmi,
449 .enable = enable_hdmi,
450 .mode = {
451 .name = "HDMI",
452 .refresh = 60,
453 .xres = 1024,
454 .yres = 768,
455 .pixclock = 15385,
456 .left_margin = 220,
457 .right_margin = 40,
458 .upper_margin = 21,
459 .lower_margin = 7,
460 .hsync_len = 60,
461 .vsync_len = 10,
462 .sync = FB_SYNC_EXT,
463 .vmode = FB_VMODE_NONINTERLACED
464} }, {
465 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
466 .bus = 2,
467 .addr = 0x4,
468 .pixfmt = IPU_PIX_FMT_LVDS666,
469 .detect = detect_i2c,
470 .enable = enable_lvds,
471 .mode = {
472 .name = "Hannstar-XGA",
473 .refresh = 60,
474 .xres = 1024,
475 .yres = 768,
476 .pixclock = 15385,
477 .left_margin = 220,
478 .right_margin = 40,
479 .upper_margin = 21,
480 .lower_margin = 7,
481 .hsync_len = 60,
482 .vsync_len = 10,
483 .sync = FB_SYNC_EXT,
484 .vmode = FB_VMODE_NONINTERLACED
485} } };
486size_t display_count = ARRAY_SIZE(displays);
487
488static void setup_display(void)
489{
490 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
491 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
492 int reg;
493
494 enable_ipu_clock();
495 imx_setup_hdmi();
496 /* Turn on LDB0,IPU,IPU DI0 clocks */
497 reg = __raw_readl(&mxc_ccm->CCGR3);
498 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
499 writel(reg, &mxc_ccm->CCGR3);
500
501 /* set LDB0, LDB1 clk select to 011/011 */
502 reg = readl(&mxc_ccm->cs2cdr);
503 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
504 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
505 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
506 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
507 writel(reg, &mxc_ccm->cs2cdr);
508
509 reg = readl(&mxc_ccm->cscmr2);
510 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
511 writel(reg, &mxc_ccm->cscmr2);
512
513 reg = readl(&mxc_ccm->chsccdr);
514 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
515 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
516 writel(reg, &mxc_ccm->chsccdr);
517
518 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
519 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
520 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
521 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
522 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
523 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
524 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
525 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
526 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
527 writel(reg, &iomux->gpr[2]);
528
529 reg = readl(&iomux->gpr[3]);
530 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
531 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
532 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
533 writel(reg, &iomux->gpr[3]);
534
535 /* Backlight CABEN on LVDS connector */
d9d41492 536 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
7a278f9f
TH		 537 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
538}
539#endif /* CONFIG_VIDEO_IPUV3 */
540
59189a8b
TH		 541/*
542 * Baseboard specific GPIO
543 */
544
545/* common to add baseboards */
546static iomux_v3_cfg_t const gw_gpio_pads[] = {
547 /* MSATA_EN */
d9d41492 548 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
59189a8b 549 /* RS232_EN# */
d9d41492 550 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
59189a8b
TH		 551};
552
553/* prototype */
554static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
555 /* PANLEDG# */
d9d41492 556 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
59189a8b 557 /* PANLEDR# */
d9d41492 558 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
59189a8b 559 /* LOCLED# */
d9d41492 560 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
59189a8b 561 /* RS485_EN */
d9d41492 562 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
59189a8b 563 /* IOEXP_PWREN# */
d9d41492 564 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
59189a8b 565 /* IOEXP_IRQ# */
d9d41492 566 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
59189a8b 567 /* VID_EN */
d9d41492 568 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
59189a8b 569 /* DIOI2C_DIS# */
d9d41492 570 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
59189a8b 571 /* PCICK_SSON */
d9d41492 572 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
59189a8b 573 /* PCI_RST# */
d9d41492 574 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
59189a8b
TH		 575};
576
577static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
578 /* PANLEDG# */
d9d41492 579 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
59189a8b 580 /* PANLEDR# */
d9d41492 581 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
59189a8b 582 /* IOEXP_PWREN# */
d9d41492 583 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
59189a8b 584 /* IOEXP_IRQ# */
d9d41492 585 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
59189a8b
TH		 586
587 /* GPS_SHDN */
d9d41492 588 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
59189a8b 589 /* VID_PWR */
d9d41492 590 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
59189a8b 591 /* PCI_RST# */
d9d41492 592 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
6a165904
TH		 593 /* PCIESKT_WDIS# */
594 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
59189a8b
TH		 595};
596
597static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
598 /* PANLEDG# */
d9d41492 599 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
59189a8b 600 /* PANLEDR# */
d9d41492 601 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
59189a8b 602 /* IOEXP_PWREN# */
d9d41492 603 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
59189a8b 604 /* IOEXP_IRQ# */
d9d41492 605 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
59189a8b
TH		 606
607 /* MX6_LOCLED# */
d9d41492 608 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
59189a8b 609 /* GPS_SHDN */
d9d41492 610 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
59189a8b 611 /* USBOTG_SEL */
d9d41492 612 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
59189a8b 613 /* VID_PWR */
d9d41492 614 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
59189a8b 615 /* PCI_RST# */
d9d41492 616 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
6a165904
TH		 617 /* PCIESKT_WDIS# */
618 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
59189a8b
TH		 619};
620
621static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
622 /* PANLEDG# */
d9d41492 623 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
59189a8b 624 /* PANLEDR# */
d9d41492 625 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
3aa22674
TH		 626 /* MX6_LOCLED# */
627 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
59189a8b 628 /* IOEXP_PWREN# */
d9d41492 629 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
59189a8b 630 /* IOEXP_IRQ# */
d9d41492 631 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
2cb6e529 632 /* DIOI2C_DIS# */
d9d41492 633 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
59189a8b 634 /* GPS_SHDN */
d9d41492 635 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
59189a8b 636 /* VID_EN */
d9d41492 637 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
59189a8b 638 /* PCI_RST# */
d9d41492 639 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
6a165904
TH		 640 /* PCIESKT_WDIS# */
641 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
59189a8b
TH		 642};
643
644static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
645 /* PANLEDG# */
d9d41492 646 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
59189a8b 647 /* PANLEDR# */
d9d41492 648 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
59189a8b 649 /* MX6_LOCLED# */
d9d41492 650 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
59189a8b 651 /* MIPI_DIO */
d9d41492 652 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
59189a8b 653 /* RS485_EN */
d9d41492 654 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
59189a8b 655 /* IOEXP_PWREN# */
d9d41492 656 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
59189a8b 657 /* IOEXP_IRQ# */
d9d41492 658 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
59189a8b 659 /* DIOI2C_DIS# */
d9d41492 660 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
59189a8b 661 /* PCICK_SSON */
d9d41492 662 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
59189a8b 663 /* PCI_RST# */
d9d41492 664 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
b40833d8 665 /* VID_EN */
d9d41492 666 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
6a165904
TH		 667 /* PCIESKT_WDIS# */
668 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
59189a8b
TH		 669};
670
3aa22674
TH		 671static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
672 /* PANLEDG# */
673 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
674 /* PANLEDR# */
675 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
676 /* MX6_LOCLED# */
677 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
678 /* PCI_RST# */
679 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
680 /* MX6_DIO[4:9] */
681 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
682 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
683 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
684 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
685 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
686 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
687 /* PCIEGBE1_OFF# */
688 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
689 /* PCIEGBE2_OFF# */
690 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
691 /* PCIESKT_WDIS# */
692 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
693};
694
59189a8b
TH		 695/*
696 * each baseboard has 4 user configurable Digital IO lines which can
697 * be pinmuxed as a GPIO or in some cases a PWM
698 */
699struct dio_cfg {
680e8db4 700 iomux_v3_cfg_t gpio_padmux[2];
59189a8b 701 unsigned gpio_param;
680e8db4 702 iomux_v3_cfg_t pwm_padmux[2];
59189a8b
TH		 703 unsigned pwm_param;
704};
705
706struct ventana {
707 /* pinmux */
708 iomux_v3_cfg_t const *gpio_pads;
709 int num_pads;
710 /* DIO pinmux/val */
711 struct dio_cfg dio_cfg[4];
712 /* various gpios (0 if non-existent) */
713 int leds[3];
714 int pcie_rst;
715 int mezz_pwren;
716 int mezz_irq;
717 int rs485en;
718 int gps_shdn;
719 int vidin_en;
720 int dioi2c_en;
721 int pcie_sson;
722 int usb_sel;
6a165904 723 int wdis;
59189a8b
TH		 724};
725
726struct ventana gpio_cfg[] = {
727 /* GW5400proto */
728 {
729 .gpio_pads = gw54xx_gpio_pads,
680e8db4 730 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
59189a8b 731 .dio_cfg = {
680e8db4
TH		 732 {
733 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
734 IMX_GPIO_NR(1, 9),
735 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
736 1
737 },
738 {
739 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
740 IMX_GPIO_NR(1, 19),
741 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
742 2
743 },
744 {
745 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
746 IMX_GPIO_NR(2, 9),
747 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
748 3
749 },
750 {
751 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
752 IMX_GPIO_NR(2, 10),
753 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
754 4
755 },
59189a8b
TH		 756 },
757 .leds = {
758 IMX_GPIO_NR(4, 6),
759 IMX_GPIO_NR(4, 10),
760 IMX_GPIO_NR(4, 15),
761 },
762 .pcie_rst = IMX_GPIO_NR(1, 29),
763 .mezz_pwren = IMX_GPIO_NR(4, 7),
764 .mezz_irq = IMX_GPIO_NR(4, 9),
765 .rs485en = IMX_GPIO_NR(3, 24),
766 .dioi2c_en = IMX_GPIO_NR(4, 5),
767 .pcie_sson = IMX_GPIO_NR(1, 20),
768 },
769
770 /* GW51xx */
771 {
772 .gpio_pads = gw51xx_gpio_pads,
680e8db4 773 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
59189a8b 774 .dio_cfg = {
680e8db4
TH		 775 {
776 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
777 IMX_GPIO_NR(1, 16),
778 { 0, 0 },
779 0
780 },
781 {
782 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
783 IMX_GPIO_NR(1, 19),
784 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
785 2
786 },
787 {
788 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
789 IMX_GPIO_NR(1, 17),
790 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
791 3
792 },
793 {
794 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
795 IMX_GPIO_NR(1, 18),
796 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
797 4
798 },
59189a8b
TH		 799 },
800 .leds = {
801 IMX_GPIO_NR(4, 6),
802 IMX_GPIO_NR(4, 10),
803 },
804 .pcie_rst = IMX_GPIO_NR(1, 0),
805 .mezz_pwren = IMX_GPIO_NR(2, 19),
806 .mezz_irq = IMX_GPIO_NR(2, 18),
807 .gps_shdn = IMX_GPIO_NR(1, 2),
808 .vidin_en = IMX_GPIO_NR(5, 20),
6a165904 809 .wdis = IMX_GPIO_NR(7, 12),
59189a8b
TH		 810 },
811
812 /* GW52xx */
813 {
814 .gpio_pads = gw52xx_gpio_pads,
680e8db4 815 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
59189a8b 816 .dio_cfg = {
680e8db4
TH		 817 {
818 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
819 IMX_GPIO_NR(1, 16),
820 { 0, 0 },
821 0
822 },
823 {
824 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
825 IMX_GPIO_NR(1, 19),
826 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
827 2
828 },
829 {
830 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
831 IMX_GPIO_NR(1, 17),
832 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
833 3
834 },
835 {
836 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
837 IMX_GPIO_NR(1, 20),
838 { 0, 0 },
839 0
840 },
59189a8b
TH		 841 },
842 .leds = {
843 IMX_GPIO_NR(4, 6),
844 IMX_GPIO_NR(4, 7),
845 IMX_GPIO_NR(4, 15),
846 },
847 .pcie_rst = IMX_GPIO_NR(1, 29),
848 .mezz_pwren = IMX_GPIO_NR(2, 19),
849 .mezz_irq = IMX_GPIO_NR(2, 18),
850 .gps_shdn = IMX_GPIO_NR(1, 27),
851 .vidin_en = IMX_GPIO_NR(3, 31),
852 .usb_sel = IMX_GPIO_NR(1, 2),
6a165904 853 .wdis = IMX_GPIO_NR(7, 12),
59189a8b
TH		 854 },
855
856 /* GW53xx */
857 {
858 .gpio_pads = gw53xx_gpio_pads,
680e8db4 859 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
59189a8b 860 .dio_cfg = {
680e8db4
TH		 861 {
862 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
863 IMX_GPIO_NR(1, 16),
864 { 0, 0 },
865 0
866 },
867 {
868 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
869 IMX_GPIO_NR(1, 19),
870 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
871 2
872 },
873 {
874 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
875 IMX_GPIO_NR(1, 17),
876 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
877 3
878 },
879 {
880 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
881 IMX_GPIO_NR(1, 20),
882 { 0, 0 },
883 0
884 },
59189a8b
TH		 885 },
886 .leds = {
887 IMX_GPIO_NR(4, 6),
888 IMX_GPIO_NR(4, 7),
889 IMX_GPIO_NR(4, 15),
890 },
891 .pcie_rst = IMX_GPIO_NR(1, 29),
892 .mezz_pwren = IMX_GPIO_NR(2, 19),
893 .mezz_irq = IMX_GPIO_NR(2, 18),
894 .gps_shdn = IMX_GPIO_NR(1, 27),
895 .vidin_en = IMX_GPIO_NR(3, 31),
6a165904 896 .wdis = IMX_GPIO_NR(7, 12),
59189a8b
TH		 897 },
898
899 /* GW54xx */
900 {
901 .gpio_pads = gw54xx_gpio_pads,
680e8db4 902 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
59189a8b 903 .dio_cfg = {
680e8db4
TH		 904 {
905 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
906 IMX_GPIO_NR(1, 9),
907 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
908 1
909 },
910 {
911 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
912 IMX_GPIO_NR(1, 19),
913 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
914 2
915 },
916 {
917 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
918 IMX_GPIO_NR(2, 9),
919 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
920 3
921 },
922 {
923 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
924 IMX_GPIO_NR(2, 10),
925 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
926 4
927 },
59189a8b
TH		 928 },
929 .leds = {
930 IMX_GPIO_NR(4, 6),
931 IMX_GPIO_NR(4, 7),
932 IMX_GPIO_NR(4, 15),
933 },
934 .pcie_rst = IMX_GPIO_NR(1, 29),
935 .mezz_pwren = IMX_GPIO_NR(2, 19),
936 .mezz_irq = IMX_GPIO_NR(2, 18),
937 .rs485en = IMX_GPIO_NR(7, 1),
938 .vidin_en = IMX_GPIO_NR(3, 31),
939 .dioi2c_en = IMX_GPIO_NR(4, 5),
940 .pcie_sson = IMX_GPIO_NR(1, 20),
6a165904 941 .wdis = IMX_GPIO_NR(5, 17),
59189a8b 942 },
3aa22674
TH		 943
944 /* GW552x */
945 {
946 .gpio_pads = gw552x_gpio_pads,
947 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
948 .dio_cfg = {
949 {
950 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
951 IMX_GPIO_NR(1, 16),
952 { 0, 0 },
953 0
954 },
955 {
956 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
957 IMX_GPIO_NR(1, 19),
958 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
959 2
960 },
961 {
962 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
963 IMX_GPIO_NR(1, 17),
964 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
965 3
966 },
967 {
968 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
969 IMX_GPIO_NR(2, 10),
970 { 0, 0 },
971 0
972 },
973 },
974 .leds = {
975 IMX_GPIO_NR(4, 6),
976 IMX_GPIO_NR(4, 7),
977 IMX_GPIO_NR(4, 15),
978 },
979 .pcie_rst = IMX_GPIO_NR(1, 29),
980 },
59189a8b
TH		 981};
982
234d89da
TH		 983/* setup board specific PMIC */
984int power_init_board(void)
985{
986 struct pmic *p;
987 u32 reg;
988
989 /* configure PFUZE100 PMIC */
990 if (board_type == GW54xx || board_type == GW54proto) {
9c0fe83e 991 power_pfuze100_init(CONFIG_I2C_PMIC);
676ac24e 992 p = pmic_get("PFUZE100");
234d89da
TH		 993 if (p && !pmic_probe(p)) {
994 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
995 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
996
997 /* Set VGEN1 to 1.5V and enable */
998 pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
999 reg &= ~(LDO_VOL_MASK);
1000 reg |= (LDOA_1_50V | LDO_EN);
1001 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1002
1003 /* Set SWBST to 5.0V and enable */
1004 pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1005 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1006 reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1007 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1008 }
1009 }
1010
1011 /* configure LTC3676 PMIC */
1012 else {
9c0fe83e 1013 power_ltc3676_init(CONFIG_I2C_PMIC);
234d89da
TH		 1014 p = pmic_get("LTC3676_PMIC");
1015 if (p && !pmic_probe(p)) {
1016 puts("PMIC: LTC3676\n");
1017 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
1018 if (is_cpu_type(MXC_CPU_MX6Q)) {
1019 /* mask PGOOD during SW1 transition */
1020 reg = 0x1d | LTC3676_PGOOD_MASK;
1021 pmic_reg_write(p, LTC3676_DVB1B, reg);
1022 /* set SW1 (VDD_SOC) to 1259mV */
1023 reg = 0x1d;
1024 pmic_reg_write(p, LTC3676_DVB1A, reg);
1025
1026 /* mask PGOOD during SW3 transition */
1027 reg = 0x1d | LTC3676_PGOOD_MASK;
1028 pmic_reg_write(p, LTC3676_DVB3B, reg);
1029 /*set SW3 (VDD_ARM) to 1259mV */
1030 reg = 0x1d;
1031 pmic_reg_write(p, LTC3676_DVB3A, reg);
1032 }
1033 }
1034 }
1035
1036 return 0;
1037}
1038
59189a8b
TH		 1039/* setup GPIO pinmux and default configuration per baseboard */
1040static void setup_board_gpio(int board)
1041{
1042 struct ventana_board_info *info = &ventana_info;
1043 const char *s;
1044 char arg[10];
1045 size_t len;
1046 int i;
1047 int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1048
1049 if (board >= GW_UNKNOWN)
1050 return;
1051
1052 /* RS232_EN# */
1053 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1054
1055 /* MSATA Enable */
1056 if (is_cpu_type(MXC_CPU_MX6Q) &&
1057 test_bit(EECONFIG_SATA, info->config)) {
1058 gpio_direction_output(GP_MSATA_SEL,
1059 (hwconfig("msata")) ? 1 : 0);
1060 } else {
1061 gpio_direction_output(GP_MSATA_SEL, 0);
1062 }
1063
6a903211
TH		 1064#if !defined(CONFIG_CMD_PCI)
1065 /* assert PCI_RST# (released by OS when clock is valid) */
59189a8b 1066 gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
6a903211 1067#endif
59189a8b
TH		 1068
1069 /* turn off (active-high) user LED's */
dc73cbe7 1070 for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
59189a8b
TH		 1071 if (gpio_cfg[board].leds[i])
1072 gpio_direction_output(gpio_cfg[board].leds[i], 1);
1073 }
1074
1075 /* Expansion Mezzanine IO */
3aa22674
TH		 1076 if (gpio_cfg[board].mezz_pwren)
1077 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1078 if (gpio_cfg[board].mezz_irq)
1079 gpio_direction_input(gpio_cfg[board].mezz_irq);
59189a8b
TH		 1080
1081 /* RS485 Transmit Enable */
1082 if (gpio_cfg[board].rs485en)
1083 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1084
1085 /* GPS_SHDN */
1086 if (gpio_cfg[board].gps_shdn)
1087 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1088
1089 /* Analog video codec power enable */
1090 if (gpio_cfg[board].vidin_en)
1091 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1092
1093 /* DIOI2C_DIS# */
1094 if (gpio_cfg[board].dioi2c_en)
1095 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1096
1097 /* PCICK_SSON: disable spread-spectrum clock */
1098 if (gpio_cfg[board].pcie_sson)
1099 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1100
1101 /* USBOTG Select (PCISKT or FrontPanel) */
1102 if (gpio_cfg[board].usb_sel)
1103 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1104
6a165904
TH		 1105 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1106 if (gpio_cfg[board].wdis)
1107 gpio_direction_output(gpio_cfg[board].wdis, 1);
1108
59189a8b
TH		 1109 /*
1110 * Configure DIO pinmux/padctl registers
1111 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1112 */
1113 for (i = 0; i < 4; i++) {
1114 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
d9d41492 1115 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
680e8db4 1116 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
59189a8b
TH		 1117
1118 sprintf(arg, "dio%d", i);
1119 if (!hwconfig(arg))
1120 continue;
1121 s = hwconfig_subarg(arg, "padctrl", &len);
d9d41492
TH		 1122 if (s) {
1123 ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1124 & 0x1ffff) | MUX_MODE_SION;
1125 }
59189a8b
TH		 1126 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1127 if (!quiet) {
1128 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
1129 (cfg->gpio_param/32)+1,
1130 cfg->gpio_param%32,
1131 cfg->gpio_param);
1132 }
680e8db4 1133 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
d9d41492 1134 ctrl);
59189a8b
TH		 1135 gpio_direction_input(cfg->gpio_param);
1136 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1137 cfg->pwm_padmux) {
1138 if (!quiet)
1139 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
680e8db4 1140 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
59189a8b
TH		 1141 MUX_PAD_CTRL(ctrl));
1142 }
1143 }
1144
1145 if (!quiet) {
1146 if (is_cpu_type(MXC_CPU_MX6Q) &&
1147 (test_bit(EECONFIG_SATA, info->config))) {
1148 printf("MSATA: %s\n", (hwconfig("msata") ?
1149 "enabled" : "disabled"));
1150 }
1151 printf("RS232: %s\n", (hwconfig("rs232")) ?
1152 "enabled" : "disabled");
1153 }
1154}
1155
1156#if defined(CONFIG_CMD_PCI)
1157int imx6_pcie_toggle_reset(void)
1158{
1159 if (board_type < GW_UNKNOWN) {
680e8db4
TH		 1160 uint pin = gpio_cfg[board_type].pcie_rst;
1161 gpio_direction_output(pin, 0);
59189a8b 1162 mdelay(50);
680e8db4 1163 gpio_direction_output(pin, 1);
59189a8b
TH		 1164 }
1165 return 0;
1166}
dad08286
TH		 1167
1168/*
1169 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1170 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1171 * properly and assert reset for 100ms.
1172 */
1173void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1174 unsigned short vendor, unsigned short device,
1175 unsigned short class)
1176{
1177 u32 dw;
1178
1179 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1180 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1181 if (vendor == PCI_VENDOR_ID_PLX &&
1182 (device & 0xfff0) == 0x8600 &&
1183 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1184 debug("configuring PLX 860X downstream PERST#\n");
1185 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1186 dw |= 0xaaa8; /* GPIO1-7 outputs */
1187 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1188
1189 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1190 dw |= 0xfe; /* GPIO1-7 output high */
1191 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1192
1193 mdelay(100);
1194 }
1195}
59189a8b
TH		 1196#endif /* CONFIG_CMD_PCI */
1197
1198#ifdef CONFIG_SERIAL_TAG
1199/*
1200 * called when setting up ATAGS before booting kernel
1201 * populate serialnum from the following (in order of priority):
1202 * serial# env var
1203 * eeprom
1204 */
1205void get_board_serial(struct tag_serialnr *serialnr)
1206{
1207 char *serial = getenv("serial#");
1208
1209 if (serial) {
1210 serialnr->high = 0;
1211 serialnr->low = simple_strtoul(serial, NULL, 10);
1212 } else if (ventana_info.model[0]) {
1213 serialnr->high = 0;
1214 serialnr->low = ventana_info.serial;
1215 } else {
1216 serialnr->high = 0;
1217 serialnr->low = 0;
1218 }
1219}
1220#endif
1221
1222/*
1223 * Board Support
1224 */
1225
0cc11dea 1226/* called from SPL board_init_f() */
59189a8b
TH		 1227int board_early_init_f(void)
1228{
1229 setup_iomux_uart();
1230 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1231
7a278f9f
TH		 1232#if defined(CONFIG_VIDEO_IPUV3)
1233 setup_display();
1234#endif
59189a8b
TH		 1235 return 0;
1236}
1237
1238int dram_init(void)
1239{
0cc11dea 1240 gd->ram_size = imx_ddr_size();
59189a8b
TH		 1241 return 0;
1242}
1243
1244int board_init(void)
1245{
0a11d6f2 1246 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
59189a8b
TH		 1247
1248 clrsetbits_le32(&iomuxc_regs->gpr[1],
1249 IOMUXC_GPR1_OTG_ID_MASK,
1250 IOMUXC_GPR1_OTG_ID_GPIO1);
1251
1252 /* address of linux boot parameters */
1253 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1254
1255#ifdef CONFIG_CMD_NAND
1256 setup_gpmi_nand();
1257#endif
1258#ifdef CONFIG_MXC_SPI
1259 setup_spi();
1260#endif
680e8db4
TH		 1261 if (is_cpu_type(MXC_CPU_MX6Q)) {
1262 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1263 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1264 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1265 } else {
1266 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1267 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1268 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1269 }
59189a8b
TH		 1270
1271#ifdef CONFIG_CMD_SATA
1272 setup_sata();
1273#endif
1274 /* read Gateworks EEPROM into global struct (used later) */
9c0fe83e 1275 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
59189a8b
TH		 1276
1277 /* board-specifc GPIO iomux */
680e8db4 1278 SETUP_IOMUX_PADS(gw_gpio_pads);
59189a8b 1279 if (board_type < GW_UNKNOWN) {
680e8db4
TH		 1280 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1281 int count = gpio_cfg[board_type].num_pads;
1282
1283 imx_iomux_v3_setup_multiple_pads(p, count);
59189a8b
TH		 1284 }
1285
1286 return 0;
1287}
1288
1289#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1290/*
1291 * called during late init (after relocation and after board_init())
1292 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1293 * EEPROM read.
1294 */
1295int checkboard(void)
1296{
1297 struct ventana_board_info *info = &ventana_info;
1298 unsigned char buf[4];
1299 const char *p;
1300 int quiet; /* Quiet or minimal output mode */
1301
1302 quiet = 0;
1303 p = getenv("quiet");
1304 if (p)
1305 quiet = simple_strtol(p, NULL, 10);
1306 else
1307 setenv("quiet", "0");
1308
1309 puts("\nGateworks Corporation Copyright 2014\n");
1310 if (info->model[0]) {
1311 printf("Model: %s\n", info->model);
1312 printf("MFGDate: %02x-%02x-%02x%02x\n",
1313 info->mfgdate[0], info->mfgdate[1],
1314 info->mfgdate[2], info->mfgdate[3]);
1315 printf("Serial:%d\n", info->serial);
1316 } else {
1317 puts("Invalid EEPROM - board will not function fully\n");
1318 }
1319 if (quiet)
1320 return 0;
1321
1322 /* Display GSC firmware revision/CRC/status */
9c0fe83e 1323 i2c_set_bus_num(CONFIG_I2C_GSC);
59189a8b
TH		 1324 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1325 printf("GSC: v%d", buf[0]);
1326 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1327 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1328 printf(" 0x%02x", buf[0]); /* irq status */
1329 }
1330 puts("\n");
1331 }
1332 /* Display RTC */
1333 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1334 printf("RTC: %d\n",
1335 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1336 }
1337
1338 return 0;
1339}
1340#endif
1341
1342#ifdef CONFIG_CMD_BMODE
1343/*
1344 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1345 * see Table 8-11 and Table 5-9
1346 * BOOT_CFG1[7] = 1 (boot from NAND)
1347 * BOOT_CFG1[5] = 0 - raw NAND
1348 * BOOT_CFG1[4] = 0 - default pad settings
1349 * BOOT_CFG1[3:2] = 00 - devices = 1
1350 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1351 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1352 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1353 * BOOT_CFG2[0] = 0 - Reset time 12ms
1354 */
1355static const struct boot_mode board_boot_modes[] = {
1356 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1357 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1358 { NULL, 0 },
1359};
1360#endif
1361
1362/* late init */
1363int misc_init_r(void)
1364{
1365 struct ventana_board_info *info = &ventana_info;
1366 unsigned char reg;
1367
1368 /* set env vars based on EEPROM data */
1369 if (ventana_info.model[0]) {
1370 char str[16], fdt[36];
1371 char *p;
1372 const char *cputype = "";
1373 int i;
1374
1375 /*
1376 * FDT name will be prefixed with CPU type. Three versions
1377 * will be created each increasingly generic and bootloader
1378 * env scripts will try loading each from most specific to
1379 * least.
1380 */
0cc11dea
TH		 1381 if (is_cpu_type(MXC_CPU_MX6Q) ||
1382 is_cpu_type(MXC_CPU_MX6D))
59189a8b 1383 cputype = "imx6q";
0cc11dea
TH		 1384 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1385 is_cpu_type(MXC_CPU_MX6SOLO))
59189a8b 1386 cputype = "imx6dl";
a7c67d7c 1387 setenv("soctype", cputype);
63b85adc
TH		 1388 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1389 setenv("flash_layout", "large");
1390 else
1391 setenv("flash_layout", "normal");
59189a8b
TH		 1392 memset(str, 0, sizeof(str));
1393 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1394 str[i] = tolower(info->model[i]);
1395 if (!getenv("model"))
1396 setenv("model", str);
1397 if (!getenv("fdt_file")) {
1398 sprintf(fdt, "%s-%s.dtb", cputype, str);
1399 setenv("fdt_file", fdt);
1400 }
1401 p = strchr(str, '-');
1402 if (p) {
1403 *p++ = 0;
1404
1405 setenv("model_base", str);
1406 if (!getenv("fdt_file1")) {
1407 sprintf(fdt, "%s-%s.dtb", cputype, str);
1408 setenv("fdt_file1", fdt);
1409 }
3aa22674
TH		 1410 if (board_type != GW552x)
1411 str[4] = 'x';
59189a8b
TH		 1412 str[5] = 'x';
1413 str[6] = 0;
1414 if (!getenv("fdt_file2")) {
1415 sprintf(fdt, "%s-%s.dtb", cputype, str);
1416 setenv("fdt_file2", fdt);
1417 }
1418 }
1419
1420 /* initialize env from EEPROM */
1421 if (test_bit(EECONFIG_ETH0, info->config) &&
1422 !getenv("ethaddr")) {
1423 eth_setenv_enetaddr("ethaddr", info->mac0);
1424 }
1425 if (test_bit(EECONFIG_ETH1, info->config) &&
1426 !getenv("eth1addr")) {
1427 eth_setenv_enetaddr("eth1addr", info->mac1);
1428 }
1429
1430 /* board serial-number */
1431 sprintf(str, "%6d", info->serial);
1432 setenv("serial#", str);
1433 }
1434
59189a8b
TH		 1435
1436 /* setup baseboard specific GPIO pinmux and config */
1437 setup_board_gpio(board_type);
1438
1439#ifdef CONFIG_CMD_BMODE
1440 add_board_boot_modes(board_boot_modes);
1441#endif
1442
1443 /*
1444 * The Gateworks System Controller implements a boot
1445 * watchdog (always enabled) as a workaround for IMX6 boot related
1446 * errata such as:
5b94b6f6
TH		 1447 * ERR005768 - no fix scheduled
1448 * ERR006282 - fixed in silicon r1.2
59189a8b
TH		 1449 * ERR007117 - fixed in silicon r1.3
1450 * ERR007220 - fixed in silicon r1.3
5b94b6f6 1451 * ERR007926 - no fix scheduled
59189a8b
TH		 1452 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1453 *
1454 * Disable the boot watchdog and display/clear the timeout flag if set
1455 */
9c0fe83e 1456 i2c_set_bus_num(CONFIG_I2C_GSC);
59189a8b
TH		 1457 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1458 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1459 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1460 puts("Error: could not disable GSC Watchdog\n");
1461 } else {
1462 puts("Error: could not disable GSC Watchdog\n");
1463 }
1464 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1465 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
49281f4d 1466 puts("GSC boot watchdog timeout detected\n");
59189a8b
TH		 1467 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1468 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1469 }
1470 }
1471
1472 return 0;
1473}
1474
1475#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1476
59189a8b
TH		 1477/*
1478 * called prior to booting kernel or by 'fdt boardsetup' command
1479 *
1480 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1481 * - mtd partitions based on mtdparts/mtdids env
1482 * - system-serial (board serial num from EEPROM)
1483 * - board (full model from EEPROM)
1484 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1485 */
1486void ft_board_setup(void *blob, bd_t *bd)
1487{
59189a8b 1488 struct ventana_board_info *info = &ventana_info;
9c0fe83e 1489 struct ventana_eeprom_config *cfg;
59189a8b
TH		 1490 struct node_info nodes[] = {
1491 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1492 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1493 };
1494 const char *model = getenv("model");
1495
1496 if (getenv("fdt_noauto")) {
1497 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1498 return;
1499 }
1500
1501 /* Update partition nodes using info from mtdparts env var */
1502 puts(" Updating MTD partitions...\n");
1503 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1504
1505 if (!model) {
1506 puts("invalid board info: Leaving FDT fully enabled\n");
1507 return;
1508 }
1509 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1510
1511 /* board serial number */
1512 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
483a435d 1513 strlen(getenv("serial#")) + 1);
59189a8b
TH		 1514
1515 /* board (model contains model from device-tree) */
1516 fdt_setprop(blob, 0, "board", info->model,
1517 strlen((const char *)info->model) + 1);
1518
1519 /*
1520 * Peripheral Config:
1521 * remove nodes by alias path if EEPROM config tells us the
1522 * peripheral is not loaded on the board.
1523 */
9c0fe83e
TH		 1524 if (getenv("fdt_noconfig")) {
1525 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1526 return;
1527 }
1528 cfg = econfig;
1529 while (cfg->name) {
1530 if (!test_bit(cfg->bit, info->config)) {
1531 fdt_del_node_and_alias(blob, cfg->dtalias ?
1532 cfg->dtalias : cfg->name);
1533 }
1534 cfg++;
59189a8b
TH		 1535 }
1536}
1537#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1538
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