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0cc11dea TH |
1 | /* |
2 | * Copyright (C) 2014 Gateworks Corporation | |
3 | * Author: Tim Harvey <tharvey@gateworks.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <i2c.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/arch/iomux.h> | |
12 | #include <asm/arch/mx6-ddr.h> | |
13 | #include <asm/arch/mx6-pins.h> | |
14 | #include <asm/arch/sys_proto.h> | |
15 | #include <asm/imx-common/boot_mode.h> | |
16 | #include <asm/imx-common/iomux-v3.h> | |
17 | #include <asm/imx-common/mxc_i2c.h> | |
18 | #include <spl.h> | |
19 | ||
20 | #include "ventana_eeprom.h" | |
21 | ||
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
24 | #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ | |
25 | #define I2C_GSC 0 | |
26 | #define GSC_EEPROM_ADDR 0x51 | |
27 | #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ | |
28 | #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ | |
29 | #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
30 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | |
31 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) | |
32 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) | |
33 | #define CONFIG_SYS_I2C_SPEED 100000 | |
34 | ||
35 | /* I2C1: GSC */ | |
36 | static struct i2c_pads_info mx6q_i2c_pad_info0 = { | |
37 | .scl = { | |
38 | .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, | |
39 | .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, | |
40 | .gp = IMX_GPIO_NR(3, 21) | |
41 | }, | |
42 | .sda = { | |
43 | .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, | |
44 | .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, | |
45 | .gp = IMX_GPIO_NR(3, 28) | |
46 | } | |
47 | }; | |
48 | static struct i2c_pads_info mx6dl_i2c_pad_info0 = { | |
49 | .scl = { | |
50 | .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, | |
51 | .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, | |
52 | .gp = IMX_GPIO_NR(3, 21) | |
53 | }, | |
54 | .sda = { | |
55 | .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, | |
56 | .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, | |
57 | .gp = IMX_GPIO_NR(3, 28) | |
58 | } | |
59 | }; | |
60 | ||
61 | static void i2c_setup_iomux(void) | |
62 | { | |
63 | if (is_cpu_type(MXC_CPU_MX6Q)) | |
64 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); | |
65 | else | |
66 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); | |
67 | } | |
68 | ||
69 | /* configure MX6Q/DUAL mmdc DDR io registers */ | |
70 | struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { | |
71 | /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ | |
72 | .dram_sdclk_0 = 0x00020030, | |
73 | .dram_sdclk_1 = 0x00020030, | |
74 | .dram_cas = 0x00020030, | |
75 | .dram_ras = 0x00020030, | |
76 | .dram_reset = 0x00020030, | |
77 | /* SDCKE[0:1]: 100k pull-up */ | |
78 | .dram_sdcke0 = 0x00003000, | |
79 | .dram_sdcke1 = 0x00003000, | |
80 | /* SDBA2: pull-up disabled */ | |
81 | .dram_sdba2 = 0x00000000, | |
82 | /* SDODT[0:1]: 100k pull-up, 40 ohm */ | |
83 | .dram_sdodt0 = 0x00003030, | |
84 | .dram_sdodt1 = 0x00003030, | |
85 | /* SDQS[0:7]: Differential input, 40 ohm */ | |
86 | .dram_sdqs0 = 0x00000030, | |
87 | .dram_sdqs1 = 0x00000030, | |
88 | .dram_sdqs2 = 0x00000030, | |
89 | .dram_sdqs3 = 0x00000030, | |
90 | .dram_sdqs4 = 0x00000030, | |
91 | .dram_sdqs5 = 0x00000030, | |
92 | .dram_sdqs6 = 0x00000030, | |
93 | .dram_sdqs7 = 0x00000030, | |
94 | ||
95 | /* DQM[0:7]: Differential input, 40 ohm */ | |
96 | .dram_dqm0 = 0x00020030, | |
97 | .dram_dqm1 = 0x00020030, | |
98 | .dram_dqm2 = 0x00020030, | |
99 | .dram_dqm3 = 0x00020030, | |
100 | .dram_dqm4 = 0x00020030, | |
101 | .dram_dqm5 = 0x00020030, | |
102 | .dram_dqm6 = 0x00020030, | |
103 | .dram_dqm7 = 0x00020030, | |
104 | }; | |
105 | ||
106 | /* configure MX6Q/DUAL mmdc GRP io registers */ | |
107 | struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { | |
108 | /* DDR3 */ | |
109 | .grp_ddr_type = 0x000c0000, | |
110 | .grp_ddrmode_ctl = 0x00020000, | |
111 | /* disable DDR pullups */ | |
112 | .grp_ddrpke = 0x00000000, | |
113 | /* ADDR[00:16], SDBA[0:1]: 40 ohm */ | |
114 | .grp_addds = 0x00000030, | |
115 | /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ | |
116 | .grp_ctlds = 0x00000030, | |
117 | /* DATA[00:63]: Differential input, 40 ohm */ | |
118 | .grp_ddrmode = 0x00020000, | |
119 | .grp_b0ds = 0x00000030, | |
120 | .grp_b1ds = 0x00000030, | |
121 | .grp_b2ds = 0x00000030, | |
122 | .grp_b3ds = 0x00000030, | |
123 | .grp_b4ds = 0x00000030, | |
124 | .grp_b5ds = 0x00000030, | |
125 | .grp_b6ds = 0x00000030, | |
126 | .grp_b7ds = 0x00000030, | |
127 | }; | |
128 | ||
129 | /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ | |
130 | struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { | |
131 | /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ | |
132 | .dram_sdclk_0 = 0x00020030, | |
133 | .dram_sdclk_1 = 0x00020030, | |
134 | .dram_cas = 0x00020030, | |
135 | .dram_ras = 0x00020030, | |
136 | .dram_reset = 0x00020030, | |
137 | /* SDCKE[0:1]: 100k pull-up */ | |
138 | .dram_sdcke0 = 0x00003000, | |
139 | .dram_sdcke1 = 0x00003000, | |
140 | /* SDBA2: pull-up disabled */ | |
141 | .dram_sdba2 = 0x00000000, | |
142 | /* SDODT[0:1]: 100k pull-up, 40 ohm */ | |
143 | .dram_sdodt0 = 0x00003030, | |
144 | .dram_sdodt1 = 0x00003030, | |
145 | /* SDQS[0:7]: Differential input, 40 ohm */ | |
146 | .dram_sdqs0 = 0x00000030, | |
147 | .dram_sdqs1 = 0x00000030, | |
148 | .dram_sdqs2 = 0x00000030, | |
149 | .dram_sdqs3 = 0x00000030, | |
150 | .dram_sdqs4 = 0x00000030, | |
151 | .dram_sdqs5 = 0x00000030, | |
152 | .dram_sdqs6 = 0x00000030, | |
153 | .dram_sdqs7 = 0x00000030, | |
154 | ||
155 | /* DQM[0:7]: Differential input, 40 ohm */ | |
156 | .dram_dqm0 = 0x00020030, | |
157 | .dram_dqm1 = 0x00020030, | |
158 | .dram_dqm2 = 0x00020030, | |
159 | .dram_dqm3 = 0x00020030, | |
160 | .dram_dqm4 = 0x00020030, | |
161 | .dram_dqm5 = 0x00020030, | |
162 | .dram_dqm6 = 0x00020030, | |
163 | .dram_dqm7 = 0x00020030, | |
164 | }; | |
165 | ||
166 | /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ | |
167 | struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { | |
168 | /* DDR3 */ | |
169 | .grp_ddr_type = 0x000c0000, | |
170 | /* SDQS[0:7]: Differential input, 40 ohm */ | |
171 | .grp_ddrmode_ctl = 0x00020000, | |
172 | /* disable DDR pullups */ | |
173 | .grp_ddrpke = 0x00000000, | |
174 | /* ADDR[00:16], SDBA[0:1]: 40 ohm */ | |
175 | .grp_addds = 0x00000030, | |
176 | /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ | |
177 | .grp_ctlds = 0x00000030, | |
178 | /* DATA[00:63]: Differential input, 40 ohm */ | |
179 | .grp_ddrmode = 0x00020000, | |
180 | .grp_b0ds = 0x00000030, | |
181 | .grp_b1ds = 0x00000030, | |
182 | .grp_b2ds = 0x00000030, | |
183 | .grp_b3ds = 0x00000030, | |
184 | .grp_b4ds = 0x00000030, | |
185 | .grp_b5ds = 0x00000030, | |
186 | .grp_b6ds = 0x00000030, | |
187 | .grp_b7ds = 0x00000030, | |
188 | }; | |
189 | ||
190 | /* MT41K128M16JT-125 */ | |
191 | static struct mx6_ddr3_cfg mt41k128m16jt_125 = { | |
192 | .mem_speed = 1600, | |
193 | .density = 2, | |
194 | .width = 16, | |
195 | .banks = 8, | |
196 | .rowaddr = 14, | |
197 | .coladdr = 10, | |
198 | .pagesz = 2, | |
199 | .trcd = 1375, | |
200 | .trcmin = 4875, | |
201 | .trasmin = 3500, | |
202 | }; | |
203 | ||
c91e4b8b TH |
204 | /* MT41K256M16HA-125 */ |
205 | static struct mx6_ddr3_cfg mt41k256m16ha_125 = { | |
206 | .mem_speed = 1600, | |
207 | .density = 4, | |
208 | .width = 16, | |
209 | .banks = 8, | |
210 | .rowaddr = 15, | |
211 | .coladdr = 10, | |
212 | .pagesz = 2, | |
213 | .trcd = 1375, | |
214 | .trcmin = 4875, | |
215 | .trasmin = 3500, | |
216 | }; | |
217 | ||
218 | /* | |
219 | * calibration - these are the various CPU/DDR3 combinations we support | |
220 | */ | |
221 | ||
222 | static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { | |
0cc11dea | 223 | /* write leveling calibration determine */ |
c91e4b8b TH |
224 | .p0_mpwldectrl0 = 0x00190017, |
225 | .p0_mpwldectrl1 = 0x00140026, | |
0cc11dea | 226 | /* Read DQS Gating calibration */ |
c91e4b8b TH |
227 | .p0_mpdgctrl0 = 0x43380347, |
228 | .p0_mpdgctrl1 = 0x433C034D, | |
0cc11dea TH |
229 | /* Read Calibration: DQS delay relative to DQ read access */ |
230 | .p0_mprddlctl = 0x3C313539, | |
0cc11dea | 231 | /* Write Calibration: DQ/DM delay relative to DQS write access */ |
c91e4b8b TH |
232 | .p0_mpwrdlctl = 0x36393C39, |
233 | }; | |
234 | ||
235 | static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { | |
236 | /* write leveling calibration determine */ | |
237 | .p0_mpwldectrl0 = 0x003C003C, | |
238 | .p0_mpwldectrl1 = 0x001F002A, | |
239 | /* Read DQS Gating calibration */ | |
240 | .p0_mpdgctrl0 = 0x42410244, | |
241 | .p0_mpdgctrl1 = 0x4234023A, | |
242 | /* Read Calibration: DQS delay relative to DQ read access */ | |
243 | .p0_mprddlctl = 0x484A4C4B, | |
244 | /* Write Calibration: DQ/DM delay relative to DQS write access */ | |
245 | .p0_mpwrdlctl = 0x33342B32, | |
0cc11dea TH |
246 | }; |
247 | ||
c91e4b8b | 248 | static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { |
0cc11dea | 249 | /* write leveling calibration determine */ |
c91e4b8b TH |
250 | .p0_mpwldectrl0 = 0x00190017, |
251 | .p0_mpwldectrl1 = 0x00140026, | |
252 | .p1_mpwldectrl0 = 0x0021001C, | |
253 | .p1_mpwldectrl1 = 0x0011001D, | |
0cc11dea | 254 | /* Read DQS Gating calibration */ |
c91e4b8b TH |
255 | .p0_mpdgctrl0 = 0x43380347, |
256 | .p0_mpdgctrl1 = 0x433C034D, | |
257 | .p1_mpdgctrl0 = 0x032C0324, | |
258 | .p1_mpdgctrl1 = 0x03310232, | |
0cc11dea | 259 | /* Read Calibration: DQS delay relative to DQ read access */ |
c91e4b8b TH |
260 | .p0_mprddlctl = 0x3C313539, |
261 | .p1_mprddlctl = 0x37343141, | |
0cc11dea | 262 | /* Write Calibration: DQ/DM delay relative to DQS write access */ |
c91e4b8b TH |
263 | .p0_mpwrdlctl = 0x36393C39, |
264 | .p1_mpwrdlctl = 0x42344438, | |
0cc11dea | 265 | }; |
c91e4b8b TH |
266 | |
267 | static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { | |
0cc11dea TH |
268 | /* write leveling calibration determine */ |
269 | .p0_mpwldectrl0 = 0x003C003C, | |
c91e4b8b TH |
270 | .p0_mpwldectrl1 = 0x001F002A, |
271 | .p1_mpwldectrl0 = 0x00330038, | |
0cc11dea TH |
272 | .p1_mpwldectrl1 = 0x0022003F, |
273 | /* Read DQS Gating calibration */ | |
274 | .p0_mpdgctrl0 = 0x42410244, | |
c91e4b8b TH |
275 | .p0_mpdgctrl1 = 0x4234023A, |
276 | .p1_mpdgctrl0 = 0x022D022D, | |
0cc11dea TH |
277 | .p1_mpdgctrl1 = 0x021C0228, |
278 | /* Read Calibration: DQS delay relative to DQ read access */ | |
279 | .p0_mprddlctl = 0x484A4C4B, | |
280 | .p1_mprddlctl = 0x4B4D4E4B, | |
281 | /* Write Calibration: DQ/DM delay relative to DQS write access */ | |
282 | .p0_mpwrdlctl = 0x33342B32, | |
283 | .p1_mpwrdlctl = 0x3933332B, | |
284 | }; | |
285 | ||
c91e4b8b | 286 | static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { |
0cc11dea | 287 | /* write leveling calibration determine */ |
c91e4b8b TH |
288 | .p0_mpwldectrl0 = 0x001E001A, |
289 | .p0_mpwldectrl1 = 0x0026001F, | |
0cc11dea | 290 | /* Read DQS Gating calibration */ |
c91e4b8b TH |
291 | .p0_mpdgctrl0 = 0x43370349, |
292 | .p0_mpdgctrl1 = 0x032D0327, | |
0cc11dea | 293 | /* Read Calibration: DQS delay relative to DQ read access */ |
c91e4b8b | 294 | .p0_mprddlctl = 0x3D303639, |
0cc11dea | 295 | /* Write Calibration: DQ/DM delay relative to DQS write access */ |
c91e4b8b | 296 | .p0_mpwrdlctl = 0x32363934, |
0cc11dea TH |
297 | }; |
298 | ||
c91e4b8b | 299 | static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { |
0cc11dea | 300 | /* write leveling calibration determine */ |
c91e4b8b TH |
301 | .p0_mpwldectrl0 = 0X00220021, |
302 | .p0_mpwldectrl1 = 0X00200030, | |
303 | .p1_mpwldectrl0 = 0X002D0027, | |
304 | .p1_mpwldectrl1 = 0X00150026, | |
0cc11dea | 305 | /* Read DQS Gating calibration */ |
c91e4b8b TH |
306 | .p0_mpdgctrl0 = 0x43330342, |
307 | .p0_mpdgctrl1 = 0x0339034A, | |
308 | .p1_mpdgctrl0 = 0x032F0325, | |
309 | .p1_mpdgctrl1 = 0x032F022E, | |
0cc11dea | 310 | /* Read Calibration: DQS delay relative to DQ read access */ |
c91e4b8b TH |
311 | .p0_mprddlctl = 0X3A2E3437, |
312 | .p1_mprddlctl = 0X35312F3F, | |
0cc11dea | 313 | /* Write Calibration: DQ/DM delay relative to DQS write access */ |
c91e4b8b TH |
314 | .p0_mpwrdlctl = 0X33363B37, |
315 | .p1_mpwrdlctl = 0X40304239, | |
0cc11dea TH |
316 | }; |
317 | ||
c91e4b8b | 318 | static void spl_dram_init(int width, int size_mb, int board_model) |
0cc11dea | 319 | { |
c91e4b8b TH |
320 | struct mx6_ddr3_cfg *mem = NULL; |
321 | struct mx6_mmdc_calibration *calib = NULL; | |
0cc11dea TH |
322 | struct mx6_ddr_sysinfo sysinfo = { |
323 | /* width of data bus:0=16,1=32,2=64 */ | |
324 | .dsize = width/32, | |
325 | /* config for full 4GB range so that get_mem_size() works */ | |
326 | .cs_density = 32, /* 32Gb per CS */ | |
327 | /* single chip select */ | |
328 | .ncs = 1, | |
329 | .cs1_mirror = 0, | |
330 | .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ | |
331 | #ifdef RTT_NOM_120OHM | |
332 | .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ | |
333 | #else | |
334 | .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ | |
335 | #endif | |
336 | .walat = 1, /* Write additional latency */ | |
337 | .ralat = 5, /* Read additional latency */ | |
338 | .mif3_mode = 3, /* Command prediction working mode */ | |
339 | .bi_on = 1, /* Bank interleaving enabled */ | |
340 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ | |
341 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ | |
342 | }; | |
343 | ||
344 | /* | |
345 | * MMDC Calibration requires the following data: | |
346 | * mx6_mmdc_calibration - board-specific calibration (routing delays) | |
c91e4b8b | 347 | * these calibration values depend on board routing, SoC, and DDR |
0cc11dea TH |
348 | * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) |
349 | * mx6_ddr_cfg - chip specific timing/layout details | |
350 | */ | |
c91e4b8b TH |
351 | if (width == 32 && size_mb == 512) { |
352 | mem = &mt41k128m16jt_125; | |
0cc11dea | 353 | if (is_cpu_type(MXC_CPU_MX6Q)) |
c91e4b8b | 354 | calib = &mx6dq_128x32_mmdc_calib; |
0cc11dea | 355 | else |
c91e4b8b TH |
356 | calib = &mx6sdl_128x32_mmdc_calib; |
357 | debug("2gB density\n"); | |
358 | } else if (width == 64 && size_mb == 1024) { | |
359 | mem = &mt41k128m16jt_125; | |
0cc11dea | 360 | if (is_cpu_type(MXC_CPU_MX6Q)) |
c91e4b8b | 361 | calib = &mx6dq_128x64_mmdc_calib; |
0cc11dea | 362 | else |
c91e4b8b TH |
363 | calib = &mx6sdl_128x64_mmdc_calib; |
364 | debug("2gB density\n"); | |
365 | } else if (width == 32 && size_mb == 1024) { | |
366 | mem = &mt41k256m16ha_125; | |
367 | if (is_cpu_type(MXC_CPU_MX6Q)) | |
368 | calib = &mx6dq_256x32_mmdc_calib; | |
369 | debug("4gB density\n"); | |
370 | } else if (width == 64 && size_mb == 2048) { | |
371 | mem = &mt41k256m16ha_125; | |
372 | if (is_cpu_type(MXC_CPU_MX6Q)) | |
373 | calib = &mx6dq_256x64_mmdc_calib; | |
374 | debug("4gB density\n"); | |
375 | } | |
376 | ||
377 | if (!mem) { | |
378 | puts("Error: Invalid Memory Configuration\n"); | |
379 | hang(); | |
380 | } | |
381 | if (!calib) { | |
382 | puts("Error: Invalid Board Calibration Configuration\n"); | |
383 | hang(); | |
0cc11dea TH |
384 | } |
385 | ||
386 | if (is_cpu_type(MXC_CPU_MX6Q)) | |
387 | mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, | |
388 | &mx6dq_grp_ioregs); | |
389 | else | |
390 | mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, | |
391 | &mx6sdl_grp_ioregs); | |
392 | mx6_dram_cfg(&sysinfo, calib, mem); | |
393 | } | |
394 | ||
395 | /* | |
396 | * called from C runtime startup code (arch/arm/lib/crt0.S:_main) | |
397 | * - we have a stack and a place to store GD, both in SRAM | |
398 | * - no variable global data is available | |
399 | */ | |
400 | void board_init_f(ulong dummy) | |
401 | { | |
402 | struct ventana_board_info ventana_info; | |
403 | int board_model; | |
404 | ||
0cc11dea TH |
405 | /* setup AIPS and disable watchdog */ |
406 | arch_cpu_init(); | |
407 | ||
408 | /* iomux and setup of i2c */ | |
409 | board_early_init_f(); | |
410 | i2c_setup_iomux(); | |
411 | ||
412 | /* setup GP timer */ | |
413 | timer_init(); | |
414 | ||
415 | /* UART clocks enabled and gd valid - init serial console */ | |
416 | preloader_console_init(); | |
417 | ||
418 | /* read/validate EEPROM info to determine board model and SDRAM cfg */ | |
419 | board_model = read_eeprom(I2C_GSC, &ventana_info); | |
420 | ||
421 | /* provide some some default: 32bit 128MB */ | |
422 | if (GW_UNKNOWN == board_model) { | |
423 | ventana_info.sdram_width = 2; | |
424 | ventana_info.sdram_size = 3; | |
425 | } | |
426 | ||
427 | /* configure MMDC for SDRAM width/size and per-model calibration */ | |
428 | spl_dram_init(8 << ventana_info.sdram_width, | |
429 | 16 << ventana_info.sdram_size, | |
430 | board_model); | |
431 | ||
432 | /* Clear the BSS. */ | |
433 | memset(__bss_start, 0, __bss_end - __bss_start); | |
434 | ||
435 | /* load/boot image from boot device */ | |
436 | board_init_r(NULL, 0); | |
437 | } | |
438 | ||
439 | void reset_cpu(ulong addr) | |
440 | { | |
441 | } |