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2da0fc0d DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <command.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/ppc4xx-gpio.h> | |
29 | ||
30 | #include <gdsys_fpga.h> | |
31 | ||
32 | #include "../common/osd.h" | |
33 | ||
b9ab8a99 DE |
34 | #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) |
35 | #define LATCH2_MC2_PRESENT_N 0x0080 | |
36 | ||
5cb4100f DE |
37 | #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) |
38 | ||
2da0fc0d DE |
39 | enum { |
40 | UNITTYPE_VIDEO_USER = 0, | |
41 | UNITTYPE_MAIN_USER = 1, | |
42 | UNITTYPE_VIDEO_SERVER = 2, | |
43 | UNITTYPE_MAIN_SERVER = 3, | |
44 | }; | |
45 | ||
46 | enum { | |
47 | HWVER_101 = 0, | |
48 | HWVER_110 = 1, | |
49 | }; | |
50 | ||
51 | enum { | |
52 | AUDIO_NONE = 0, | |
53 | AUDIO_TX = 1, | |
54 | AUDIO_RX = 2, | |
55 | AUDIO_RXTX = 3, | |
56 | }; | |
57 | ||
58 | enum { | |
59 | SYSCLK_156250 = 2, | |
60 | }; | |
61 | ||
62 | enum { | |
63 | RAM_NONE = 0, | |
64 | RAM_DDR2_32 = 1, | |
65 | RAM_DDR2_64 = 2, | |
66 | }; | |
67 | ||
5cb4100f DE |
68 | static unsigned int get_hwver(void) |
69 | { | |
70 | u16 latch3 = in_le16((void *)LATCH3_BASE); | |
71 | ||
72 | return latch3 & 0x0003; | |
73 | } | |
74 | ||
75 | static unsigned int get_mc2_present(void) | |
76 | { | |
77 | u16 latch2 = in_le16((void *)LATCH2_BASE); | |
78 | ||
79 | return !(latch2 & LATCH2_MC2_PRESENT_N); | |
80 | } | |
81 | ||
2da0fc0d DE |
82 | static void print_fpga_info(unsigned dev) |
83 | { | |
84 | ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); | |
85 | u16 versions = in_le16(&fpga->versions); | |
86 | u16 fpga_version = in_le16(&fpga->fpga_version); | |
87 | u16 fpga_features = in_le16(&fpga->fpga_features); | |
88 | unsigned unit_type; | |
89 | unsigned hardware_version; | |
90 | unsigned feature_compression; | |
91 | unsigned feature_rs232; | |
92 | unsigned feature_audio; | |
93 | unsigned feature_sysclock; | |
94 | unsigned feature_ramconfig; | |
95 | unsigned feature_carrier_speed; | |
96 | unsigned feature_carriers; | |
97 | unsigned feature_video_channels; | |
98 | int fpga_state = get_fpga_state(dev); | |
99 | ||
100 | printf("FPGA%d: ", dev); | |
101 | ||
102 | hardware_version = versions & 0x000f; | |
103 | ||
104 | if (fpga_state | |
105 | && !((hardware_version == HWVER_101) | |
106 | && (fpga_state == FPGA_STATE_DONE_FAILED))) { | |
107 | puts("not available\n"); | |
108 | print_fpga_state(dev); | |
109 | return; | |
110 | } | |
111 | ||
112 | unit_type = (versions >> 4) & 0x000f; | |
113 | hardware_version = versions & 0x000f; | |
114 | feature_compression = (fpga_features >> 13) & 0x0003; | |
115 | feature_rs232 = fpga_features & (1<<11); | |
116 | feature_audio = (fpga_features >> 9) & 0x0003; | |
117 | feature_sysclock = (fpga_features >> 7) & 0x0003; | |
118 | feature_ramconfig = (fpga_features >> 5) & 0x0003; | |
119 | feature_carrier_speed = fpga_features & (1<<4); | |
120 | feature_carriers = (fpga_features >> 2) & 0x0003; | |
121 | feature_video_channels = fpga_features & 0x0003; | |
122 | ||
123 | switch (unit_type) { | |
124 | case UNITTYPE_VIDEO_USER: | |
125 | printf("Videochannel Userside"); | |
126 | break; | |
127 | ||
128 | case UNITTYPE_MAIN_USER: | |
129 | printf("Mainchannel Userside"); | |
130 | break; | |
131 | ||
132 | case UNITTYPE_VIDEO_SERVER: | |
133 | printf("Videochannel Serverside"); | |
134 | break; | |
135 | ||
136 | case UNITTYPE_MAIN_SERVER: | |
137 | printf("Mainchannel Serverside"); | |
138 | break; | |
139 | ||
140 | default: | |
141 | printf("UnitType %d(not supported)", unit_type); | |
142 | break; | |
143 | } | |
144 | ||
145 | switch (hardware_version) { | |
146 | case HWVER_101: | |
147 | printf(" HW-Ver 1.01\n"); | |
148 | break; | |
149 | ||
150 | case HWVER_110: | |
151 | printf(" HW-Ver 1.10\n"); | |
152 | break; | |
153 | ||
154 | default: | |
155 | printf(" HW-Ver %d(not supported)\n", | |
156 | hardware_version); | |
157 | break; | |
158 | } | |
159 | ||
160 | printf(" FPGA V %d.%02d, features:", | |
161 | fpga_version / 100, fpga_version % 100); | |
162 | ||
163 | printf(" %sRS232", feature_rs232 ? "" : "no "); | |
164 | ||
165 | switch (feature_audio) { | |
166 | case AUDIO_NONE: | |
167 | printf(", no audio"); | |
168 | break; | |
169 | ||
170 | case AUDIO_TX: | |
171 | printf(", audio tx"); | |
172 | break; | |
173 | ||
174 | case AUDIO_RX: | |
175 | printf(", audio rx"); | |
176 | break; | |
177 | ||
178 | case AUDIO_RXTX: | |
179 | printf(", audio rx+tx"); | |
180 | break; | |
181 | ||
182 | default: | |
183 | printf(", audio %d(not supported)", feature_audio); | |
184 | break; | |
185 | } | |
186 | ||
187 | switch (feature_sysclock) { | |
188 | case SYSCLK_156250: | |
189 | printf(", clock 156.25 MHz"); | |
190 | break; | |
191 | ||
192 | default: | |
193 | printf(", clock %d(not supported)", feature_sysclock); | |
194 | break; | |
195 | } | |
196 | ||
197 | puts(",\n "); | |
198 | ||
199 | switch (feature_ramconfig) { | |
200 | case RAM_NONE: | |
201 | printf("no RAM"); | |
202 | break; | |
203 | ||
204 | case RAM_DDR2_32: | |
205 | printf("RAM 32 bit DDR2"); | |
206 | break; | |
207 | ||
208 | case RAM_DDR2_64: | |
209 | printf("RAM 64 bit DDR2"); | |
210 | break; | |
211 | ||
212 | default: | |
213 | printf("RAM %d(not supported)", feature_ramconfig); | |
214 | break; | |
215 | } | |
216 | ||
217 | printf(", %d carrier(s) %s", feature_carriers, | |
218 | feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); | |
219 | ||
220 | printf(", %d video channel(s)\n", feature_video_channels); | |
221 | } | |
222 | ||
223 | /* | |
224 | * Check Board Identity: | |
225 | */ | |
226 | int checkboard(void) | |
227 | { | |
f0c0b3a9 WD |
228 | char buf[64]; |
229 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
2da0fc0d DE |
230 | |
231 | printf("Board: "); | |
232 | ||
233 | printf("DLVision 10G"); | |
234 | ||
f0c0b3a9 | 235 | if (i > 0) { |
2da0fc0d | 236 | puts(", serial# "); |
f0c0b3a9 | 237 | puts(buf); |
2da0fc0d DE |
238 | } |
239 | ||
240 | puts("\n"); | |
241 | ||
b9ab8a99 | 242 | print_fpga_info(0); |
5cb4100f | 243 | if (get_mc2_present()) |
b9ab8a99 | 244 | print_fpga_info(1); |
2da0fc0d DE |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
249 | int last_stage_init(void) | |
250 | { | |
b9ab8a99 DE |
251 | ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); |
252 | u16 versions = in_le16(&fpga->versions); | |
b9ab8a99 DE |
253 | |
254 | if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) | |
255 | return 0; | |
256 | ||
5cb4100f | 257 | if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) |
b9ab8a99 | 258 | osd_probe(0); |
2da0fc0d | 259 | |
5cb4100f DE |
260 | if (get_mc2_present() && |
261 | (!get_fpga_state(1) || (get_hwver() == HWVER_101))) | |
b9ab8a99 | 262 | osd_probe(1); |
2da0fc0d DE |
263 | |
264 | return 0; | |
265 | } |