[thirdparty/u-boot.git] / board / gdsys / 405ep / io.c

/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>

#include <dtt.h>
#include <miiphy.h>

#include "405ep.h"
#include <gdsys_fpga.h>

#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)

#define PHYREG_CONTROL				0
#define PHYREG_PAGE_ADDRESS			22
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26

enum {
	UNITTYPE_CCD_SWITCH = 1,
};

enum {
	HWVER_100 = 0,
	HWVER_110 = 1,
	HWVER_121 = 2,
	HWVER_122 = 3,
};

int misc_init_r(void)
{
	/* startup fans */
	dtt_init();

	return 0;
}

int configure_gbit_phy(unsigned char addr)
{
	unsigned short value;

	/* select page 2 */
	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
		PHYREG_PAGE_ADDRESS, 0x0002))
		goto err_out;
	/* disable SGMII autonegotiation */
	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
		PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
		goto err_out;
	/* select page 0 */
	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
		PHYREG_PAGE_ADDRESS, 0x0000))
		goto err_out;
	/* switch from powerdown to normal operation */
	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
		goto err_out;
	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
		goto err_out;
	/* reset phy so settings take effect */
	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
		PHYREG_CONTROL, 0x9140))
		goto err_out;

	return 0;

err_out:
	printf("Error writing to the PHY addr=%02x\n", addr);
	return -1;
}

/*
 * Check Board Identity:
 */
int checkboard(void)
{
	char *s = getenv("serial#");

	puts("Board: CATCenter Io");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}

	puts("\n");

	return 0;
}

static void print_fpga_info(void)
{
	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
	u16 versions = in_le16(&fpga->versions);
	u16 fpga_version = in_le16(&fpga->fpga_version);
	u16 fpga_features = in_le16(&fpga->fpga_features);
	unsigned unit_type;
	unsigned hardware_version;
	unsigned feature_channels;
	unsigned feature_expansion;

	unit_type = (versions & 0xf000) >> 12;
	hardware_version = versions & 0x000f;
	feature_channels = fpga_features & 0x007f;
	feature_expansion = fpga_features & (1<<15);

	puts("FPGA:  ");

	switch (unit_type) {
	case UNITTYPE_CCD_SWITCH:
		printf("CCD-Switch");
		break;

	default:
		printf("UnitType %d(not supported)", unit_type);
		break;
	}

	switch (hardware_version) {
	case HWVER_100:
		printf(" HW-Ver 1.00\n");
		break;

	case HWVER_110:
		printf(" HW-Ver 1.10\n");
		break;

	case HWVER_121:
		printf(" HW-Ver 1.21\n");
		break;

	case HWVER_122:
		printf(" HW-Ver 1.22\n");
		break;

	default:
		printf(" HW-Ver %d(not supported)\n",
		       hardware_version);
		break;
	}

	printf("       FPGA V %d.%02d, features:",
		fpga_version / 100, fpga_version % 100);

	printf(" %d channel(s)", feature_channels);

	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
}

/*
 * setup Gbit PHYs
 */
int last_stage_init(void)
{
	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
	unsigned int k;

	print_fpga_info();

	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
		bb_miiphy_read, bb_miiphy_write);

	for (k = 0; k < 32; ++k)
		configure_gbit_phy(k);

	/* take fpga serdes blocks out of reset */
	out_le16(&fpga->quad_serdes_reset, 0);

	return 0;
}

void gd405ep_init(void)
{
}

void gd405ep_set_fpga_reset(unsigned state)
{
	if (state) {
		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
	} else {
		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
	}
}

void gd405ep_setup_hw(void)
{
	/*
	 * set "startup-finished"-gpios
	 */
	gpio_write_bit(21, 0);
	gpio_write_bit(22, 1);
}

int gd405ep_get_fpga_done(unsigned fpga)
{
	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
}
Commit	Line	Data
a605ea7e DE	1	/*
	2	* (C) Copyright 2010
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
a605ea7e DE	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
	10	#include <asm/processor.h>
	11	#include <asm/io.h>
	12	#include <asm/ppc4xx-gpio.h>
	13
b19bf834	14	#include <dtt.h>
a605ea7e DE	15	#include <miiphy.h>
a605ea7e DE	16
6e9e6c36	17	#include "405ep.h"
2da0fc0d	18	#include <gdsys_fpga.h>
a605ea7e	19
6e9e6c36 DE	20	#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
	21	#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
	22	#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
	23
a605ea7e DE	24	#define PHYREG_CONTROL 0
	25	#define PHYREG_PAGE_ADDRESS 22
	26	#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
	27	#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
	28
a605ea7e DE	29	enum {
	30	UNITTYPE_CCD_SWITCH = 1,
	31	};
	32
	33	enum {
	34	HWVER_100 = 0,
	35	HWVER_110 = 1,
	36	HWVER_121 = 2,
	37	HWVER_122 = 3,
	38	};
	39
b19bf834 DE	40	int misc_init_r(void)
	41	{
	42	/* startup fans */
	43	dtt_init();
	44
	45	return 0;
	46	}
	47
a605ea7e DE	48	int configure_gbit_phy(unsigned char addr)
	49	{
	50	unsigned short value;
	51
	52	/* select page 2 */
	53	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
	54	PHYREG_PAGE_ADDRESS, 0x0002))
	55	goto err_out;
	56	/* disable SGMII autonegotiation */
	57	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
	58	PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
	59	goto err_out;
	60	/* select page 0 */
	61	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
	62	PHYREG_PAGE_ADDRESS, 0x0000))
	63	goto err_out;
	64	/* switch from powerdown to normal operation */
	65	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
	66	PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
	67	goto err_out;
	68	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
	69	PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
	70	goto err_out;
	71	/* reset phy so settings take effect */
	72	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
	73	PHYREG_CONTROL, 0x9140))
	74	goto err_out;
	75
	76	return 0;
	77
	78	err_out:
	79	printf("Error writing to the PHY addr=%02x\n", addr);
	80	return -1;
	81	}
	82
	83	/*
	84	* Check Board Identity:
	85	*/
	86	int checkboard(void)
	87	{
b19bf834 DE	88	char *s = getenv("serial#");
	89
	90	puts("Board: CATCenter Io");
	91
	92	if (s != NULL) {
	93	puts(", serial# ");
	94	puts(s);
	95	}
	96
	97	puts("\n");
	98
	99	return 0;
	100	}
	101
	102	static void print_fpga_info(void)
	103	{
0e60aa85	104	struct ihs_fpga fpga = (struct ihs_fpga ) CONFIG_SYS_FPGA_BASE(0);
2da0fc0d DE	105	u16 versions = in_le16(&fpga->versions);
	106	u16 fpga_version = in_le16(&fpga->fpga_version);
	107	u16 fpga_features = in_le16(&fpga->fpga_features);
a605ea7e DE	108	unsigned unit_type;
	109	unsigned hardware_version;
	110	unsigned feature_channels;
	111	unsigned feature_expansion;
	112
	113	unit_type = (versions & 0xf000) >> 12;
	114	hardware_version = versions & 0x000f;
	115	feature_channels = fpga_features & 0x007f;
	116	feature_expansion = fpga_features & (1<<15);
	117
b19bf834	118	puts("FPGA: ");
a605ea7e DE	119
	120	switch (unit_type) {
	121	case UNITTYPE_CCD_SWITCH:
	122	printf("CCD-Switch");
	123	break;
	124
	125	default:
	126	printf("UnitType %d(not supported)", unit_type);
	127	break;
	128	}
	129
	130	switch (hardware_version) {
	131	case HWVER_100:
	132	printf(" HW-Ver 1.00\n");
	133	break;
	134
	135	case HWVER_110:
	136	printf(" HW-Ver 1.10\n");
	137	break;
	138
	139	case HWVER_121:
	140	printf(" HW-Ver 1.21\n");
	141	break;
	142
	143	case HWVER_122:
	144	printf(" HW-Ver 1.22\n");
	145	break;
	146
	147	default:
	148	printf(" HW-Ver %d(not supported)\n",
	149	hardware_version);
	150	break;
	151	}
	152
	153	printf(" FPGA V %d.%02d, features:",
	154	fpga_version / 100, fpga_version % 100);
	155
	156	printf(" %d channel(s)", feature_channels);
	157
	158	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
a605ea7e DE	159	}
	160
	161	/*
	162	* setup Gbit PHYs
	163	*/
	164	int last_stage_init(void)
	165	{
0e60aa85	166	struct ihs_fpga fpga = (struct ihs_fpga ) CONFIG_SYS_FPGA_BASE(0);
a605ea7e DE	167	unsigned int k;
a605ea7e DE	168
b19bf834 DE	169	print_fpga_info();
b19bf834 DE	170
a605ea7e DE	171	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
	172	bb_miiphy_read, bb_miiphy_write);
	173
	174	for (k = 0; k < 32; ++k)
	175	configure_gbit_phy(k);
	176
	177	/* take fpga serdes blocks out of reset */
2da0fc0d	178	out_le16(&fpga->quad_serdes_reset, 0);
a605ea7e DE	179
	180	return 0;
	181	}
6e9e6c36 DE	182
	183	void gd405ep_init(void)
	184	{
	185	}
	186
	187	void gd405ep_set_fpga_reset(unsigned state)
	188	{
	189	if (state) {
	190	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
	191	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
	192	} else {
	193	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
	194	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
	195	}
	196	}
	197
	198	void gd405ep_setup_hw(void)
	199	{
	200	/*
	201	* set "startup-finished"-gpios
	202	*/
	203	gpio_write_bit(21, 0);
	204	gpio_write_bit(22, 1);
	205	}
	206
	207	int gd405ep_get_fpga_done(unsigned fpga)
	208	{
	209	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
	210	}