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a605ea7e DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a605ea7e DE |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/ppc4xx-gpio.h> | |
13 | ||
6e9e6c36 | 14 | #include "405ep.h" |
2da0fc0d | 15 | #include <gdsys_fpga.h> |
a605ea7e | 16 | |
2da0fc0d | 17 | #include "../common/osd.h" |
a605ea7e | 18 | |
6e9e6c36 DE |
19 | #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) |
20 | #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) | |
21 | #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) | |
22 | ||
a605ea7e DE |
23 | enum { |
24 | UNITTYPE_MAIN_SERVER = 0, | |
25 | UNITTYPE_MAIN_USER = 1, | |
26 | UNITTYPE_VIDEO_SERVER = 2, | |
27 | UNITTYPE_VIDEO_USER = 3, | |
28 | }; | |
29 | ||
30 | enum { | |
31 | HWVER_100 = 0, | |
32 | HWVER_104 = 1, | |
33 | HWVER_110 = 2, | |
34 | }; | |
35 | ||
36 | enum { | |
37 | COMPRESSION_NONE = 0, | |
38 | COMPRESSION_TYPE1_DELTA, | |
39 | }; | |
40 | ||
41 | enum { | |
42 | AUDIO_NONE = 0, | |
43 | AUDIO_TX = 1, | |
44 | AUDIO_RX = 2, | |
45 | AUDIO_RXTX = 3, | |
46 | }; | |
47 | ||
48 | enum { | |
49 | SYSCLK_147456 = 0, | |
50 | }; | |
51 | ||
52 | enum { | |
53 | RAM_DDR2_32 = 0, | |
54 | }; | |
55 | ||
aba27acf DE |
56 | struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; |
57 | ||
a605ea7e DE |
58 | /* |
59 | * Check Board Identity: | |
60 | */ | |
61 | int checkboard(void) | |
62 | { | |
b19bf834 DE |
63 | char *s = getenv("serial#"); |
64 | ||
65 | puts("Board: "); | |
66 | ||
67 | puts("IoCon"); | |
68 | ||
69 | if (s != NULL) { | |
70 | puts(", serial# "); | |
71 | puts(s); | |
72 | } | |
73 | ||
74 | puts("\n"); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static void print_fpga_info(void) | |
80 | { | |
aba27acf DE |
81 | u16 versions; |
82 | u16 fpga_version; | |
83 | u16 fpga_features; | |
a605ea7e DE |
84 | unsigned unit_type; |
85 | unsigned hardware_version; | |
86 | unsigned feature_compression; | |
87 | unsigned feature_osd; | |
88 | unsigned feature_audio; | |
89 | unsigned feature_sysclock; | |
90 | unsigned feature_ramconfig; | |
91 | unsigned feature_carriers; | |
92 | unsigned feature_video_channels; | |
93 | ||
aba27acf DE |
94 | FPGA_GET_REG(0, versions, &versions); |
95 | FPGA_GET_REG(0, fpga_version, &fpga_version); | |
96 | FPGA_GET_REG(0, fpga_features, &fpga_features); | |
97 | ||
a605ea7e DE |
98 | unit_type = (versions & 0xf000) >> 12; |
99 | hardware_version = versions & 0x000f; | |
100 | feature_compression = (fpga_features & 0xe000) >> 13; | |
101 | feature_osd = fpga_features & (1<<11); | |
102 | feature_audio = (fpga_features & 0x0600) >> 9; | |
103 | feature_sysclock = (fpga_features & 0x0180) >> 7; | |
104 | feature_ramconfig = (fpga_features & 0x0060) >> 5; | |
105 | feature_carriers = (fpga_features & 0x000c) >> 2; | |
106 | feature_video_channels = fpga_features & 0x0003; | |
107 | ||
a605ea7e DE |
108 | switch (unit_type) { |
109 | case UNITTYPE_MAIN_USER: | |
110 | printf("Mainchannel"); | |
111 | break; | |
112 | ||
113 | case UNITTYPE_VIDEO_USER: | |
114 | printf("Videochannel"); | |
115 | break; | |
116 | ||
117 | default: | |
118 | printf("UnitType %d(not supported)", unit_type); | |
119 | break; | |
120 | } | |
121 | ||
122 | switch (hardware_version) { | |
123 | case HWVER_100: | |
124 | printf(" HW-Ver 1.00\n"); | |
125 | break; | |
126 | ||
127 | case HWVER_104: | |
128 | printf(" HW-Ver 1.04\n"); | |
129 | break; | |
130 | ||
131 | case HWVER_110: | |
132 | printf(" HW-Ver 1.10\n"); | |
133 | break; | |
134 | ||
135 | default: | |
136 | printf(" HW-Ver %d(not supported)\n", | |
137 | hardware_version); | |
138 | break; | |
139 | } | |
140 | ||
141 | printf(" FPGA V %d.%02d, features:", | |
142 | fpga_version / 100, fpga_version % 100); | |
143 | ||
144 | ||
145 | switch (feature_compression) { | |
146 | case COMPRESSION_NONE: | |
147 | printf(" no compression"); | |
148 | break; | |
149 | ||
150 | case COMPRESSION_TYPE1_DELTA: | |
151 | printf(" type1-deltacompression"); | |
152 | break; | |
153 | ||
154 | default: | |
155 | printf(" compression %d(not supported)", feature_compression); | |
156 | break; | |
157 | } | |
158 | ||
159 | printf(", %sosd", feature_osd ? "" : "no "); | |
160 | ||
161 | switch (feature_audio) { | |
162 | case AUDIO_NONE: | |
163 | printf(", no audio"); | |
164 | break; | |
165 | ||
166 | case AUDIO_TX: | |
167 | printf(", audio tx"); | |
168 | break; | |
169 | ||
170 | case AUDIO_RX: | |
171 | printf(", audio rx"); | |
172 | break; | |
173 | ||
174 | case AUDIO_RXTX: | |
175 | printf(", audio rx+tx"); | |
176 | break; | |
177 | ||
178 | default: | |
179 | printf(", audio %d(not supported)", feature_audio); | |
180 | break; | |
181 | } | |
182 | ||
183 | puts(",\n "); | |
184 | ||
185 | switch (feature_sysclock) { | |
186 | case SYSCLK_147456: | |
187 | printf("clock 147.456 MHz"); | |
188 | break; | |
189 | ||
190 | default: | |
191 | printf("clock %d(not supported)", feature_sysclock); | |
192 | break; | |
193 | } | |
194 | ||
195 | switch (feature_ramconfig) { | |
196 | case RAM_DDR2_32: | |
197 | printf(", RAM 32 bit DDR2"); | |
198 | break; | |
199 | ||
200 | default: | |
201 | printf(", RAM %d(not supported)", feature_ramconfig); | |
202 | break; | |
203 | } | |
204 | ||
205 | printf(", %d carrier(s)", feature_carriers); | |
206 | ||
207 | printf(", %d video channel(s)\n", feature_video_channels); | |
a605ea7e DE |
208 | } |
209 | ||
210 | int last_stage_init(void) | |
211 | { | |
b19bf834 DE |
212 | print_fpga_info(); |
213 | ||
2da0fc0d | 214 | return osd_probe(0); |
a605ea7e DE |
215 | } |
216 | ||
217 | /* | |
218 | * provide access to fpga gpios (for I2C bitbang) | |
aba27acf | 219 | * (these may look all too simple but make iocon.h much more readable) |
a605ea7e DE |
220 | */ |
221 | void fpga_gpio_set(int pin) | |
222 | { | |
aba27acf | 223 | FPGA_SET_REG(0, gpio.set, pin); |
a605ea7e DE |
224 | } |
225 | ||
226 | void fpga_gpio_clear(int pin) | |
227 | { | |
aba27acf | 228 | FPGA_SET_REG(0, gpio.clear, pin); |
a605ea7e DE |
229 | } |
230 | ||
231 | int fpga_gpio_get(int pin) | |
232 | { | |
aba27acf DE |
233 | u16 val; |
234 | ||
235 | FPGA_GET_REG(0, gpio.read, &val); | |
236 | ||
237 | return val & pin; | |
a605ea7e | 238 | } |
6e9e6c36 DE |
239 | |
240 | void gd405ep_init(void) | |
241 | { | |
242 | } | |
243 | ||
244 | void gd405ep_set_fpga_reset(unsigned state) | |
245 | { | |
246 | if (state) { | |
247 | out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); | |
248 | out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); | |
249 | } else { | |
250 | out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); | |
251 | out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); | |
252 | } | |
253 | } | |
254 | ||
255 | void gd405ep_setup_hw(void) | |
256 | { | |
257 | /* | |
258 | * set "startup-finished"-gpios | |
259 | */ | |
260 | gpio_write_bit(21, 0); | |
261 | gpio_write_bit(22, 1); | |
262 | } | |
263 | ||
264 | int gd405ep_get_fpga_done(unsigned fpga) | |
265 | { | |
266 | return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); | |
267 | } |