[people/ms/u-boot.git] / board / gdsys / 405ep / neo.c

/*
 * (C) Copyright 2011
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <dtt.h>

#include "405ep.h"
#include <gdsys_fpga.h>

#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)

enum {
	UNITTYPE_CCX16 = 1,
	UNITTYPE_CCIP216 = 2,
};

enum {
	HWVER_300 = 3,
};

struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;

int misc_init_r(void)
{
	/* startup fans */
	dtt_init();

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	puts("Board: CATCenter Neo");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}

	puts("\n");

	return 0;
}

static void print_fpga_info(void)
{
	u16 versions;
	u16 fpga_version;
	u16 fpga_features;
	int fpga_state = get_fpga_state(0);
	unsigned unit_type;
	unsigned hardware_version;
	unsigned feature_channels;

	puts("FPGA:  ");
	if (fpga_state & FPGA_STATE_DONE_FAILED) {
		printf(" done timed out\n");
		return;
	}

	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
		printf(" refelectione test failed\n");
		return;
	}

	FPGA_GET_REG(0, versions, &versions);
	FPGA_GET_REG(0, fpga_version, &fpga_version);
	FPGA_GET_REG(0, fpga_features, &fpga_features);

	unit_type = (versions & 0xf000) >> 12;
	hardware_version = versions & 0x000f;
	feature_channels = fpga_features & 0x007f;

	switch (unit_type) {
	case UNITTYPE_CCX16:
		printf("CCX-Switch");
		break;

	default:
		printf("UnitType %d(not supported)", unit_type);
		break;
	}

	switch (hardware_version) {
	case HWVER_300:
		printf(" HW-Ver 3.00-3.12\n");
		break;

	default:
		printf(" HW-Ver %d(not supported)\n",
		       hardware_version);
		break;
	}

	printf("       FPGA V %d.%02d, features:",
		fpga_version / 100, fpga_version % 100);

	printf(" %d channel(s)\n", feature_channels);
}

int last_stage_init(void)
{
	print_fpga_info();

	return 0;
}

void gd405ep_init(void)
{
}

void gd405ep_set_fpga_reset(unsigned state)
{
	if (state) {
		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
	} else {
		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
	}
}

void gd405ep_setup_hw(void)
{
	/*
	 * set "startup-finished"-gpios
	 */
	gpio_write_bit(21, 0);
	gpio_write_bit(22, 1);
}

int gd405ep_get_fpga_done(unsigned fpga)
{
	/*
	 * Neo hardware has no FPGA-DONE GPIO
	 */
	return 1;
}
Commit	Line	Data
6e9e6c36 DE	1	/*
	2	* (C) Copyright 2011
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
6e9e6c36 DE	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
	10	#include <asm/processor.h>
	11	#include <asm/io.h>
	12	#include <asm/ppc4xx-gpio.h>
	13	#include <dtt.h>
	14
	15	#include "405ep.h"
	16	#include <gdsys_fpga.h>
	17
	18	#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
	19	#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
	20	#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
	21
	22	enum {
	23	UNITTYPE_CCX16 = 1,
	24	UNITTYPE_CCIP216 = 2,
	25	};
	26
	27	enum {
	28	HWVER_300 = 3,
	29	};
	30
aba27acf DE	31	struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
aba27acf DE	32
6e9e6c36 DE	33	int misc_init_r(void)
	34	{
	35	/* startup fans */
	36	dtt_init();
	37
	38	return 0;
	39	}
	40
	41	int checkboard(void)
	42	{
	43	char *s = getenv("serial#");
	44
	45	puts("Board: CATCenter Neo");
	46
	47	if (s != NULL) {
	48	puts(", serial# ");
	49	puts(s);
	50	}
	51
	52	puts("\n");
	53
	54	return 0;
	55	}
	56
	57	static void print_fpga_info(void)
	58	{
aba27acf DE	59	u16 versions;
	60	u16 fpga_version;
	61	u16 fpga_features;
6e9e6c36 DE	62	int fpga_state = get_fpga_state(0);
	63	unsigned unit_type;
	64	unsigned hardware_version;
	65	unsigned feature_channels;
	66
	67	puts("FPGA: ");
	68	if (fpga_state & FPGA_STATE_DONE_FAILED) {
	69	printf(" done timed out\n");
	70	return;
	71	}
	72
	73	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
	74	printf(" refelectione test failed\n");
	75	return;
	76	}
	77
aba27acf DE	78	FPGA_GET_REG(0, versions, &versions);
	79	FPGA_GET_REG(0, fpga_version, &fpga_version);
	80	FPGA_GET_REG(0, fpga_features, &fpga_features);
	81
6e9e6c36 DE	82	unit_type = (versions & 0xf000) >> 12;
	83	hardware_version = versions & 0x000f;
	84	feature_channels = fpga_features & 0x007f;
	85
	86	switch (unit_type) {
	87	case UNITTYPE_CCX16:
	88	printf("CCX-Switch");
	89	break;
	90
	91	default:
	92	printf("UnitType %d(not supported)", unit_type);
	93	break;
	94	}
	95
	96	switch (hardware_version) {
	97	case HWVER_300:
	98	printf(" HW-Ver 3.00-3.12\n");
	99	break;
	100
	101	default:
	102	printf(" HW-Ver %d(not supported)\n",
	103	hardware_version);
	104	break;
	105	}
	106
	107	printf(" FPGA V %d.%02d, features:",
	108	fpga_version / 100, fpga_version % 100);
	109
	110	printf(" %d channel(s)\n", feature_channels);
	111	}
	112
	113	int last_stage_init(void)
	114	{
	115	print_fpga_info();
	116
	117	return 0;
	118	}
	119
	120	void gd405ep_init(void)
	121	{
	122	}
	123
	124	void gd405ep_set_fpga_reset(unsigned state)
	125	{
	126	if (state) {
	127	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
	128	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
	129	} else {
	130	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
	131	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
	132	}
	133	}
	134
	135	void gd405ep_setup_hw(void)
	136	{
	137	/*
	138	* set "startup-finished"-gpios
	139	*/
	140	gpio_write_bit(21, 0);
	141	gpio_write_bit(22, 1);
	142	}
	143
	144	int gd405ep_get_fpga_done(unsigned fpga)
	145	{
146	/*
147	* Neo hardware has no FPGA-DONE GPIO
148	*/
149	return 1;
150	}