[thirdparty/u-boot.git] / board / gdsys / common / miiphybb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 */

#include <common.h>
#include <miiphy.h>

#include <asm/io.h>

struct io_bb_pinset {
	int mdio;
	int mdc;
};

static int io_bb_mii_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct io_bb_pinset *pins = bus->priv;

	out_be32((void *)GPIO0_TCR,
		in_be32((void *)GPIO0_TCR) | pins->mdio);

	return 0;
}

static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct io_bb_pinset *pins = bus->priv;

	out_be32((void *)GPIO0_TCR,
		in_be32((void *)GPIO0_TCR) & ~pins->mdio);

	return 0;
}

static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct io_bb_pinset *pins = bus->priv;

	if (v)
		out_be32((void *)GPIO0_OR,
			in_be32((void *)GPIO0_OR) | pins->mdio);
	else
		out_be32((void *)GPIO0_OR,
			in_be32((void *)GPIO0_OR) & ~pins->mdio);

	return 0;
}

static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct io_bb_pinset *pins = bus->priv;

	*v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);

	return 0;
}

static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct io_bb_pinset *pins = bus->priv;

	if (v)
		out_be32((void *)GPIO0_OR,
			in_be32((void *)GPIO0_OR) | pins->mdc);
	else
		out_be32((void *)GPIO0_OR,
			in_be32((void *)GPIO0_OR) & ~pins->mdc);

	return 0;
}

static int io_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(1);

	return 0;
}

struct io_bb_pinset io_bb_pinsets[] = {
	{
		.mdio = CONFIG_SYS_MDIO_PIN,
		.mdc = CONFIG_SYS_MDC_PIN,
	},
#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
	{
		.mdio = CONFIG_SYS_MDIO1_PIN,
		.mdc = CONFIG_SYS_MDC1_PIN,
	},
#endif
};

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name = CONFIG_SYS_GBIT_MII_BUSNAME,
		.init = io_bb_mii_init,
		.mdio_active = io_bb_mdio_active,
		.mdio_tristate = io_bb_mdio_tristate,
		.set_mdio = io_bb_set_mdio,
		.get_mdio = io_bb_get_mdio,
		.set_mdc = io_bb_set_mdc,
		.delay = io_bb_delay,
		.priv = &io_bb_pinsets[0],
	},
#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
	{
		.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
		.init = io_bb_mii_init,
		.mdio_active = io_bb_mdio_active,
		.mdio_tristate = io_bb_mdio_tristate,
		.set_mdio = io_bb_set_mdio,
		.get_mdio = io_bb_get_mdio,
		.set_mdc = io_bb_set_mdc,
		.delay = io_bb_delay,
		.priv = &io_bb_pinsets[1],
	},
#endif
};

int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
			  sizeof(bb_miiphy_buses[0]);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a605ea7e DE	2	/*
a605ea7e DE	3	* (C) Copyright 2010
d38826a3	4	* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
a605ea7e DE	5	*/
	6
	7	#include <common.h>
	8	#include <miiphy.h>
	9
	10	#include <asm/io.h>
	11
255ef4d9 DE	12	struct io_bb_pinset {
	13	int mdio;
	14	int mdc;
	15	};
	16
a605ea7e DE	17	static int io_bb_mii_init(struct bb_miiphy_bus *bus)
	18	{
	19	return 0;
	20	}
	21
	22	static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
	23	{
255ef4d9 DE	24	struct io_bb_pinset *pins = bus->priv;
255ef4d9 DE	25
a605ea7e	26	out_be32((void *)GPIO0_TCR,
255ef4d9	27	in_be32((void *)GPIO0_TCR) \| pins->mdio);
a605ea7e DE	28
	29	return 0;
	30	}
	31
	32	static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	33	{
255ef4d9 DE	34	struct io_bb_pinset *pins = bus->priv;
255ef4d9 DE	35
a605ea7e	36	out_be32((void *)GPIO0_TCR,
255ef4d9	37	in_be32((void *)GPIO0_TCR) & ~pins->mdio);
a605ea7e DE	38
	39	return 0;
	40	}
	41
	42	static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	43	{
255ef4d9 DE	44	struct io_bb_pinset *pins = bus->priv;
255ef4d9 DE	45
a605ea7e DE	46	if (v)
a605ea7e DE	47	out_be32((void *)GPIO0_OR,
255ef4d9	48	in_be32((void *)GPIO0_OR) \| pins->mdio);
a605ea7e DE	49	else
a605ea7e DE	50	out_be32((void *)GPIO0_OR,
255ef4d9	51	in_be32((void *)GPIO0_OR) & ~pins->mdio);
a605ea7e DE	52
	53	return 0;
	54	}
	55
	56	static int io_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	57	{
255ef4d9 DE	58	struct io_bb_pinset *pins = bus->priv;
	59
	60	v = ((in_be32((void )GPIO0_IR) & pins->mdio) != 0);
a605ea7e DE	61
	62	return 0;
	63	}
	64
	65	static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	66	{
255ef4d9 DE	67	struct io_bb_pinset *pins = bus->priv;
255ef4d9 DE	68
a605ea7e DE	69	if (v)
a605ea7e DE	70	out_be32((void *)GPIO0_OR,
255ef4d9	71	in_be32((void *)GPIO0_OR) \| pins->mdc);
a605ea7e DE	72	else
a605ea7e DE	73	out_be32((void *)GPIO0_OR,
255ef4d9	74	in_be32((void *)GPIO0_OR) & ~pins->mdc);
a605ea7e DE	75
	76	return 0;
	77	}
	78
	79	static int io_bb_delay(struct bb_miiphy_bus *bus)
	80	{
	81	udelay(1);
	82
	83	return 0;
	84	}
	85
255ef4d9 DE	86	struct io_bb_pinset io_bb_pinsets[] = {
	87	{
	88	.mdio = CONFIG_SYS_MDIO_PIN,
	89	.mdc = CONFIG_SYS_MDC_PIN,
	90	},
	91	#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
	92	{
	93	.mdio = CONFIG_SYS_MDIO1_PIN,
	94	.mdc = CONFIG_SYS_MDC1_PIN,
	95	},
	96	#endif
	97	};
	98
a605ea7e DE	99	struct bb_miiphy_bus bb_miiphy_buses[] = {
	100	{
	101	.name = CONFIG_SYS_GBIT_MII_BUSNAME,
	102	.init = io_bb_mii_init,
	103	.mdio_active = io_bb_mdio_active,
	104	.mdio_tristate = io_bb_mdio_tristate,
	105	.set_mdio = io_bb_set_mdio,
	106	.get_mdio = io_bb_get_mdio,
	107	.set_mdc = io_bb_set_mdc,
	108	.delay = io_bb_delay,
255ef4d9 DE	109	.priv = &io_bb_pinsets[0],
	110	},
	111	#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
	112	{
	113	.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
	114	.init = io_bb_mii_init,
	115	.mdio_active = io_bb_mdio_active,
	116	.mdio_tristate = io_bb_mdio_tristate,
	117	.set_mdio = io_bb_set_mdio,
	118	.get_mdio = io_bb_get_mdio,
	119	.set_mdc = io_bb_set_mdc,
	120	.delay = io_bb_delay,
	121	.priv = &io_bb_pinsets[1],
	122	},
	123	#endif
a605ea7e DE	124	};
	125
	126	int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
	127	sizeof(bb_miiphy_buses[0]);