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ab4c62c1 DE |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
5 | * Based on board/amcc/canyonlands/canyonlands.c | |
6 | * (C) Copyright 2008 | |
7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
ab4c62c1 DE |
10 | */ |
11 | ||
12 | #include <common.h> | |
b36df561 | 13 | #include <asm/ppc440.h> |
ab4c62c1 DE |
14 | #include <libfdt.h> |
15 | #include <fdt_support.h> | |
16 | #include <i2c.h> | |
17 | #include <asm/processor.h> | |
18 | #include <asm/io.h> | |
19 | #include <asm/mmu.h> | |
20 | #include <asm/4xx_pcie.h> | |
09887762 | 21 | #include <asm/ppc4xx-gpio.h> |
ab4c62c1 DE |
22 | |
23 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; | |
24 | ||
25 | DECLARE_GLOBAL_DATA_PTR; | |
26 | ||
27 | #define CONFIG_SYS_BCSR3_PCIE 0x10 | |
28 | ||
29 | int board_early_init_f(void) | |
30 | { | |
ab4c62c1 DE |
31 | /* |
32 | * Setup the interrupt controller polarities, triggers, etc. | |
33 | */ | |
952e7760 SR |
34 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
35 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
36 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ | |
37 | mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ | |
38 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ | |
39 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
40 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
ab4c62c1 | 41 | |
952e7760 SR |
42 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
43 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
44 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
45 | mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ | |
46 | mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ | |
47 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
48 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
ab4c62c1 | 49 | |
952e7760 SR |
50 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
51 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
52 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
53 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ | |
54 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ | |
55 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
56 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
ab4c62c1 | 57 | |
952e7760 SR |
58 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
59 | mtdcr(UIC3ER, 0x00000000); /* disable all */ | |
60 | mtdcr(UIC3CR, 0x00000000); /* all non-critical */ | |
61 | mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ | |
62 | mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ | |
63 | mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ | |
64 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ | |
ab4c62c1 DE |
65 | |
66 | /* | |
67 | * Configure PFC (Pin Function Control) registers | |
68 | * enable GPIO 49-63 | |
69 | * UART0: 4 pins | |
70 | */ | |
71 | mtsdr(SDR0_PFC0, 0x00007fff); | |
72 | mtsdr(SDR0_PFC1, 0x00040000); | |
73 | ||
74 | /* Enable PCI host functionality in SDR0_PCI0 */ | |
75 | mtsdr(SDR0_PCI0, 0xe0000000); | |
76 | ||
77 | mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ | |
78 | ||
79 | /* Setup PLB4-AHB bridge based on the system address map */ | |
80 | mtdcr(AHB_TOP, 0x8000004B); | |
81 | mtdcr(AHB_BOT, 0x8000004B); | |
82 | ||
56bdfa96 DE |
83 | /* |
84 | * Configure USB-STP pins as alternate and not GPIO | |
85 | * It seems to be neccessary to configure the STP pins as GPIO | |
86 | * input at powerup (perhaps while USB reset is asserted). So | |
87 | * we configure those pins to their "real" function now. | |
88 | */ | |
89 | gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); | |
90 | gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); | |
ab4c62c1 DE |
91 | |
92 | /* Trigger board component reset */ | |
93 | out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); | |
94 | out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff); | |
95 | udelay(50); | |
96 | out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf); | |
97 | out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf); | |
98 | udelay(50); | |
99 | out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); | |
100 | out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | int get_cpu_num(void) | |
106 | { | |
107 | int cpu = NA_OR_UNKNOWN_CPU; | |
108 | ||
109 | return cpu; | |
110 | } | |
111 | ||
112 | int checkboard(void) | |
113 | { | |
f0c0b3a9 WD |
114 | char buf[64]; |
115 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
ab4c62c1 DE |
116 | |
117 | #ifdef CONFIG_DEVCONCENTER | |
118 | printf("Board: DevCon-Center"); | |
119 | #else | |
4c188367 | 120 | printf("Board: Intip"); |
ab4c62c1 DE |
121 | #endif |
122 | ||
f0c0b3a9 | 123 | if (i > 0) { |
ab4c62c1 | 124 | puts(", serial# "); |
f0c0b3a9 | 125 | puts(buf); |
ab4c62c1 DE |
126 | } |
127 | putc('\n'); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
ab4c62c1 DE |
132 | int board_early_init_r(void) |
133 | { | |
134 | /* | |
135 | * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH | |
136 | * (Spansion 29GL512), but the boot EBC mapping only supports a maximum | |
137 | * of 16MBytes (4.ff00.0000 - 4.ffff.ffff). | |
138 | * To solve this problem, the FLASH has to get remapped to another | |
139 | * EBC address which accepts bigger regions: | |
140 | * | |
141 | * 0xfn00.0000 -> 4.cn00.0000 | |
142 | */ | |
143 | ||
144 | u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ? | |
145 | EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB; | |
146 | ||
147 | /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */ | |
d1c3b275 | 148 | mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L |
ab4c62c1 DE |
149 | | bxcr_bw |
150 | | EBC_BXCR_BU_RW | |
151 | | EBC_BXCR_BW_16BIT); | |
152 | ||
153 | /* Remove TLB entry of boot EBC mapping */ | |
154 | remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); | |
155 | ||
156 | /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */ | |
157 | program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, | |
158 | CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); | |
159 | ||
160 | /* | |
161 | * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address | |
162 | * 0xfc00.0000 is possible | |
163 | */ | |
164 | ||
165 | /* | |
166 | * Clear potential errors resulting from auto-calibration. | |
167 | * If not done, then we could get an interrupt later on when | |
168 | * exceptions are enabled. | |
169 | */ | |
170 | set_mcsr(get_mcsr()); | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | int misc_init_r(void) | |
176 | { | |
177 | u32 sdr0_srst1 = 0; | |
178 | u32 eth_cfg; | |
ab4c62c1 DE |
179 | |
180 | /* | |
181 | * Set EMAC mode/configuration (GMII, SGMII, RGMII...). | |
182 | * This is board specific, so let's do it here. | |
183 | */ | |
184 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
185 | /* disable SGMII mode */ | |
186 | eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | | |
187 | SDR0_ETH_CFG_SGMII1_ENABLE | | |
188 | SDR0_ETH_CFG_SGMII0_ENABLE); | |
189 | /* Set the for 2 RGMII mode */ | |
190 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
191 | eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; | |
56bdfa96 | 192 | eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; |
ab4c62c1 DE |
193 | mtsdr(SDR0_ETH_CFG, eth_cfg); |
194 | ||
195 | /* | |
196 | * The AHB Bridge core is held in reset after power-on or reset | |
197 | * so enable it now | |
198 | */ | |
199 | mfsdr(SDR0_SRST1, sdr0_srst1); | |
200 | sdr0_srst1 &= ~SDR0_SRST1_AHB; | |
201 | mtsdr(SDR0_SRST1, sdr0_srst1); | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
7ffe3cd6 | 206 | #ifdef CONFIG_OF_BOARD_SETUP |
ab4c62c1 DE |
207 | extern void __ft_board_setup(void *blob, bd_t *bd); |
208 | ||
e895a4b0 | 209 | int ft_board_setup(void *blob, bd_t *bd) |
ab4c62c1 DE |
210 | { |
211 | __ft_board_setup(blob, bd); | |
212 | ||
213 | fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", | |
214 | "disabled", sizeof("disabled"), 1); | |
215 | ||
216 | fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", | |
217 | "disabled", sizeof("disabled"), 1); | |
e895a4b0 SG |
218 | |
219 | return 0; | |
ab4c62c1 | 220 | } |
7ffe3cd6 | 221 | #endif /* CONFIG_OF_BOARD_SETUP */ |