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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
6b0071c1 PST |
2 | /* |
3 | * (C) Copyright 2015 General Electric Company | |
6b0071c1 PST |
4 | */ |
5 | ||
6 | #ifndef __PPD_GPIO_H_ | |
7 | #define __PPD_GPIO_H_ | |
8 | ||
9 | #include <asm/arch/iomux-mx53.h> | |
10 | #include <asm/gpio.h> | |
11 | ||
12 | #define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ | |
13 | PAD_CTL_PUS_100K_UP) | |
14 | ||
15 | static const iomux_v3_cfg_t ppd_pads[] = { | |
16 | /* FEC */ | |
17 | MX53_PAD_EIM_A22__GPIO2_16, | |
18 | /* UART */ | |
19 | NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL), | |
20 | NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL), | |
21 | /* Video */ | |
22 | MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */ | |
23 | MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */ | |
24 | MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */ | |
25 | MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */ | |
26 | MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */ | |
27 | MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */ | |
28 | MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ | |
29 | MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */ | |
30 | MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */ | |
31 | /* I2C */ | |
32 | MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */ | |
33 | ||
34 | /* SPI */ | |
35 | MX53_PAD_DISP0_DAT23__GPIO5_17, | |
36 | MX53_PAD_KEY_COL2__GPIO4_10, | |
37 | MX53_PAD_KEY_ROW2__GPIO4_11, | |
38 | MX53_PAD_KEY_COL3__GPIO4_12, | |
39 | }; | |
40 | ||
41 | struct gpio_cfg { | |
42 | unsigned int gpio; | |
43 | int value; | |
44 | }; | |
45 | ||
46 | #define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16) | |
47 | #define UD_SCAN_CTRL IMX_GPIO_NR(5, 21) | |
48 | #define LR_SCAN_CTRL IMX_GPIO_NR(5, 20) | |
49 | #define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3) | |
50 | #define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2) | |
51 | #define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18) | |
52 | #define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28) | |
53 | #define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28) | |
54 | #define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29) | |
55 | #define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22) | |
56 | #define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27) | |
57 | #define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17) | |
58 | #define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29) | |
59 | #define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18) | |
60 | #define ECSPI1_CS0 IMX_GPIO_NR(5, 17) | |
61 | #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) | |
62 | #define ECSPI1_CS2 IMX_GPIO_NR(4, 11) | |
63 | #define ECSPI1_CS3 IMX_GPIO_NR(4, 12) | |
64 | ||
65 | static const struct gpio_cfg ppd_gpios[] = { | |
66 | /* FEC */ | |
67 | /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */ | |
68 | /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */ | |
69 | { RESET_IMX535_ETHERNET_PHY_N, 0 }, | |
70 | { RESET_IMX535_ETHERNET_PHY_N, 1 }, | |
71 | /* Video */ | |
72 | { UD_SCAN_CTRL, 0 }, | |
73 | { LR_SCAN_CTRL, 1 }, | |
74 | #ifdef PROPRIETARY_CHANGES | |
75 | { LVDS0_MUX_CTRL, 1 }, | |
76 | #else | |
77 | { LVDS0_MUX_CTRL, 0 }, | |
78 | #endif | |
79 | { LVDS1_MUX_CTRL, 1 }, | |
80 | { HOST_CONTROLLED_RESET_TO_LCD_N, 1 }, | |
81 | { DATA_WIDTH_CTRL, 0 }, | |
82 | { RESET_DP0_TRANSMITTER_N, 1 }, | |
83 | { RESET_DP1_TRANSMITTER_N, 1 }, | |
84 | { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 }, | |
85 | { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 }, | |
86 | { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 }, | |
87 | { BACKLIGHT_ENABLE, 0 }, | |
88 | { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 }, | |
89 | { ECSPI1_CS0, 1 }, | |
90 | { ECSPI1_CS1, 1 }, | |
91 | { ECSPI1_CS2, 1 }, | |
92 | { ECSPI1_CS3, 1 }, | |
93 | }; | |
94 | ||
95 | #endif /* __PPD_GPIO_H_ */ |