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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * Keith Outwater, keith_outwater@mvis.com. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | * | |
24 | */ | |
25 | ||
26 | /* | |
27 | * Virtex2 FPGA configuration support for the GEN860T computer | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <virtex2.h> | |
32 | #include <command.h> | |
33 | #include "fpga.h" | |
34 | ||
d87080b7 WD |
35 | DECLARE_GLOBAL_DATA_PTR; |
36 | ||
0133502e | 37 | #if defined(CONFIG_FPGA) |
c609719b WD |
38 | |
39 | #if 0 | |
40 | #define GEN860T_FPGA_DEBUG | |
41 | #endif | |
42 | ||
43 | #ifdef GEN860T_FPGA_DEBUG | |
44 | #define PRINTF(fmt,args...) printf (fmt ,##args) | |
45 | #else | |
46 | #define PRINTF(fmt,args...) | |
47 | #endif | |
48 | ||
49 | /* | |
50 | * Port bit numbers for the Selectmap controls | |
51 | */ | |
52 | #define FPGA_INIT_BIT_NUM 22 /* PB22 */ | |
53 | #define FPGA_RESET_BIT_NUM 11 /* PC11 */ | |
54 | #define FPGA_DONE_BIT_NUM 16 /* PB16 */ | |
55 | #define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */ | |
56 | ||
57 | /* Note that these are pointers to code that is in Flash. They will be | |
58 | * relocated at runtime. | |
59 | */ | |
60 | Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { | |
61 | fpga_pre_config_fn, | |
62 | fpga_pgm_fn, | |
63 | fpga_init_fn, | |
64 | fpga_err_fn, | |
65 | fpga_done_fn, | |
66 | fpga_clk_fn, | |
67 | fpga_cs_fn, | |
68 | fpga_wr_fn, | |
69 | fpga_read_data_fn, | |
70 | fpga_write_data_fn, | |
71 | fpga_busy_fn, | |
72 | fpga_abort_fn, | |
73 | fpga_post_config_fn | |
74 | }; | |
75 | ||
76 | Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { | |
bf9e3b38 WD |
77 | {Xilinx_Virtex2, |
78 | slave_selectmap, | |
79 | XILINX_XC2V3000_SIZE, | |
80 | (void *) &fpga_fns, | |
81 | 0} | |
c609719b WD |
82 | }; |
83 | ||
84 | /* | |
85 | * Display FPGA revision information | |
86 | */ | |
bf9e3b38 | 87 | void print_fpga_revision (void) |
c609719b | 88 | { |
bf9e3b38 WD |
89 | vu_long *rev_p = (vu_long *) 0x60000008; |
90 | ||
91 | printf ("FPGA Revision 0x%.8lx" | |
92 | " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", | |
93 | *rev_p, | |
94 | ((*rev_p >> 28) & 0xf), | |
95 | ((*rev_p >> 20) & 0xff), | |
96 | ((*rev_p >> 12) & 0xff), | |
97 | ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); | |
c609719b WD |
98 | } |
99 | ||
100 | ||
101 | /* | |
102 | * Perform a simple test of the FPGA to processor interface using the FPGA's | |
103 | * inverting bus test register. The great thing about doing a read/write | |
104 | * test on a register that inverts it's contents is that you avoid any | |
105 | * problems with bus charging. | |
106 | * Return 0 on failure, 1 on success. | |
107 | */ | |
bf9e3b38 | 108 | int test_fpga_ibtr (void) |
c609719b | 109 | { |
bf9e3b38 | 110 | vu_long *ibtr_p = (vu_long *) 0x60000010; |
c609719b WD |
111 | vu_long readback; |
112 | vu_long compare; | |
113 | int i; | |
114 | int j; | |
115 | int k; | |
116 | int pass = 1; | |
117 | ||
118 | static const ulong bitpattern[] = { | |
bf9e3b38 WD |
119 | 0xdeadbeef, /* magic ID pattern for debug */ |
120 | 0x00000001, /* single bit */ | |
121 | 0x00000003, /* two adjacent bits */ | |
122 | 0x00000007, /* three adjacent bits */ | |
123 | 0x0000000F, /* four adjacent bits */ | |
124 | 0x00000005, /* two non-adjacent bits */ | |
125 | 0x00000015, /* three non-adjacent bits */ | |
126 | 0x00000055, /* four non-adjacent bits */ | |
127 | 0xaaaaaaaa, /* alternating 1/0 */ | |
c609719b WD |
128 | }; |
129 | ||
130 | for (i = 0; i < 1024; i++) { | |
131 | for (j = 0; j < 31; j++) { | |
bf9e3b38 WD |
132 | for (k = 0; |
133 | k < sizeof (bitpattern) / sizeof (bitpattern[0]); | |
134 | k++) { | |
c609719b WD |
135 | *ibtr_p = compare = (bitpattern[k] << j); |
136 | readback = *ibtr_p; | |
137 | if (readback != ~compare) { | |
bf9e3b38 | 138 | printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); |
c609719b WD |
139 | pass = 0; |
140 | break; | |
141 | } | |
142 | } | |
bf9e3b38 WD |
143 | if (!pass) |
144 | break; | |
c609719b | 145 | } |
bf9e3b38 WD |
146 | if (!pass) |
147 | break; | |
c609719b WD |
148 | } |
149 | if (pass) { | |
bf9e3b38 WD |
150 | printf ("FPGA inverting bus test passed\n"); |
151 | print_fpga_revision (); | |
152 | } else { | |
153 | printf ("** FPGA inverting bus test failed\n"); | |
c609719b WD |
154 | } |
155 | return pass; | |
156 | } | |
157 | ||
158 | ||
159 | /* | |
160 | * Set the active-low FPGA reset signal. | |
161 | */ | |
bf9e3b38 | 162 | void fpga_reset (int assert) |
c609719b | 163 | { |
bf9e3b38 | 164 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
c609719b | 165 | |
bf9e3b38 | 166 | PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); |
c609719b WD |
167 | if (assert) { |
168 | immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); | |
bf9e3b38 WD |
169 | PRINTF ("asserted\n"); |
170 | } else { | |
c609719b | 171 | immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); |
bf9e3b38 | 172 | PRINTF ("deasserted\n"); |
c609719b WD |
173 | } |
174 | } | |
175 | ||
176 | ||
177 | /* | |
178 | * Initialize the SelectMap interface. We assume that the mode and the | |
179 | * initial state of all of the port pins have already been set! | |
180 | */ | |
bf9e3b38 | 181 | void fpga_selectmap_init (void) |
c609719b | 182 | { |
bf9e3b38 WD |
183 | PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, |
184 | __LINE__); | |
185 | fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */ | |
c609719b WD |
186 | } |
187 | ||
188 | ||
189 | /* | |
190 | * Initialize the fpga. Return 1 on success, 0 on failure. | |
191 | */ | |
bf9e3b38 | 192 | int gen860t_init_fpga (void) |
c609719b | 193 | { |
c609719b WD |
194 | int i; |
195 | ||
bf9e3b38 WD |
196 | PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); |
197 | fpga_init (gd->reloc_off); | |
198 | fpga_selectmap_init (); | |
c609719b | 199 | |
bf9e3b38 WD |
200 | for (i = 0; i < CONFIG_FPGA_COUNT; i++) { |
201 | PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); | |
202 | fpga_add (fpga_xilinx, &fpga[i]); | |
c609719b | 203 | } |
bf9e3b38 | 204 | return 1; |
c609719b WD |
205 | } |
206 | ||
207 | ||
208 | /* | |
209 | * Set the FPGA's active-low SelectMap program line to the specified level | |
210 | */ | |
bf9e3b38 | 211 | int fpga_pgm_fn (int assert, int flush, int cookie) |
c609719b | 212 | { |
bf9e3b38 | 213 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
c609719b | 214 | |
bf9e3b38 | 215 | PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); |
c609719b WD |
216 | |
217 | if (assert) { | |
bf9e3b38 WD |
218 | immap->im_ioport.iop_padat &= |
219 | ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); | |
220 | PRINTF ("asserted\n"); | |
221 | } else { | |
222 | immap->im_ioport.iop_padat |= | |
223 | (0x8000 >> FPGA_PROGRAM_BIT_NUM); | |
224 | PRINTF ("deasserted\n"); | |
c609719b WD |
225 | } |
226 | return assert; | |
227 | } | |
228 | ||
229 | ||
230 | /* | |
231 | * Test the state of the active-low FPGA INIT line. Return 1 on INIT | |
232 | * asserted (low). | |
233 | */ | |
bf9e3b38 | 234 | int fpga_init_fn (int cookie) |
c609719b | 235 | { |
bf9e3b38 | 236 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
c609719b | 237 | |
bf9e3b38 WD |
238 | PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); |
239 | if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { | |
240 | PRINTF ("high\n"); | |
c609719b | 241 | return 0; |
bf9e3b38 WD |
242 | } else { |
243 | PRINTF ("low\n"); | |
c609719b WD |
244 | return 1; |
245 | } | |
246 | } | |
247 | ||
248 | ||
249 | /* | |
250 | * Test the state of the active-high FPGA DONE pin | |
251 | */ | |
bf9e3b38 | 252 | int fpga_done_fn (int cookie) |
c609719b | 253 | { |
bf9e3b38 | 254 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
c609719b | 255 | |
bf9e3b38 | 256 | PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); |
c609719b | 257 | if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { |
bf9e3b38 | 258 | PRINTF ("high\n"); |
c609719b | 259 | return FPGA_SUCCESS; |
bf9e3b38 WD |
260 | } else { |
261 | PRINTF ("low\n"); | |
c609719b WD |
262 | return FPGA_FAIL; |
263 | } | |
264 | } | |
265 | ||
266 | ||
267 | /* | |
268 | * Read FPGA SelectMap data. | |
269 | */ | |
bf9e3b38 | 270 | int fpga_read_data_fn (unsigned char *data, int cookie) |
c609719b | 271 | { |
bf9e3b38 | 272 | vu_char *p = (vu_char *) SELECTMAP_BASE; |
c609719b WD |
273 | |
274 | *data = *p; | |
275 | #if 0 | |
bf9e3b38 | 276 | PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); |
c609719b | 277 | #endif |
bf9e3b38 | 278 | return (int) data; |
c609719b WD |
279 | } |
280 | ||
281 | ||
282 | /* | |
283 | * Write data to the FPGA SelectMap port | |
284 | */ | |
bf9e3b38 | 285 | int fpga_write_data_fn (unsigned char data, int flush, int cookie) |
c609719b | 286 | { |
bf9e3b38 | 287 | vu_char *p = (vu_char *) SELECTMAP_BASE; |
c609719b WD |
288 | |
289 | #if 0 | |
bf9e3b38 | 290 | PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); |
c609719b WD |
291 | #endif |
292 | *p = data; | |
bf9e3b38 | 293 | return (int) data; |
c609719b WD |
294 | } |
295 | ||
296 | ||
297 | /* | |
298 | * Abort and FPGA operation | |
299 | */ | |
bf9e3b38 | 300 | int fpga_abort_fn (int cookie) |
c609719b | 301 | { |
bf9e3b38 WD |
302 | PRINTF ("%s:%d: FPGA program sequence aborted\n", |
303 | __FUNCTION__, __LINE__); | |
c609719b WD |
304 | return FPGA_FAIL; |
305 | } | |
306 | ||
307 | ||
308 | /* | |
309 | * FPGA pre-configuration function. Just make sure that | |
310 | * FPGA reset is asserted to keep the FPGA from starting up after | |
311 | * configuration. | |
312 | */ | |
bf9e3b38 | 313 | int fpga_pre_config_fn (int cookie) |
c609719b | 314 | { |
bf9e3b38 WD |
315 | PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); |
316 | fpga_reset (TRUE); | |
c609719b WD |
317 | return 0; |
318 | } | |
319 | ||
320 | ||
321 | /* | |
322 | * FPGA post configuration function. Blip the FPGA reset line and then see if | |
323 | * the FPGA appears to be running. | |
324 | */ | |
bf9e3b38 | 325 | int fpga_post_config_fn (int cookie) |
c609719b WD |
326 | { |
327 | int rc; | |
328 | ||
bf9e3b38 WD |
329 | PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); |
330 | fpga_reset (TRUE); | |
331 | udelay (1000); | |
332 | fpga_reset (FALSE); | |
c609719b WD |
333 | udelay (1000); |
334 | ||
335 | /* | |
336 | * Use the FPGA,s inverting bus test register to do a simple test of the | |
337 | * processor interface. | |
338 | */ | |
bf9e3b38 | 339 | rc = test_fpga_ibtr (); |
c609719b WD |
340 | return rc; |
341 | } | |
342 | ||
343 | ||
344 | /* | |
345 | * Clock, chip select and write signal assert functions and error check | |
346 | * and busy functions. These are only stubs because the GEN860T selectmap | |
347 | * interface handles sequencing of control signals automatically (it uses | |
348 | * a memory-mapped interface to the FPGA SelectMap port). The design of | |
349 | * the interface guarantees that the SelectMap port cannot be overrun so | |
350 | * no busy check is needed. A configuration error is signalled by INIT | |
351 | * going low during configuration, so there is no need for a separate error | |
352 | * function. | |
353 | */ | |
bf9e3b38 | 354 | int fpga_clk_fn (int assert_clk, int flush, int cookie) |
c609719b WD |
355 | { |
356 | return assert_clk; | |
357 | } | |
358 | ||
bf9e3b38 | 359 | int fpga_cs_fn (int assert_cs, int flush, int cookie) |
c609719b WD |
360 | { |
361 | return assert_cs; | |
362 | } | |
363 | ||
bf9e3b38 | 364 | int fpga_wr_fn (int assert_write, int flush, int cookie) |
c609719b WD |
365 | { |
366 | return assert_write; | |
367 | } | |
368 | ||
bf9e3b38 | 369 | int fpga_err_fn (int cookie) |
c609719b WD |
370 | { |
371 | return 0; | |
372 | } | |
373 | ||
bf9e3b38 | 374 | int fpga_busy_fn (int cookie) |
c609719b WD |
375 | { |
376 | return 0; | |
377 | } | |
378 | #endif |