[people/ms/u-boot.git] / board / gen860t / gen860t.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Keith Outwater, keith_outwater@mvis.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <virtex2.h>
#include <common.h>
#include <mpc8xx.h>
#include <asm/8xx_immap.h>
#include "beeper.h"
#include "fpga.h"
#include "ioport.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif

#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
#include <net.h>
#endif

#if 0
#define GEN860T_DEBUG
#endif

#ifdef GEN860T_DEBUG
#define	PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define	PRINTF(fmt,args...)
#endif

/*
 * The following UPM init tables were generated automatically by
 * Motorola's MCUINIT program. See the README file for UPM to
 * SDRAM pin assignments if you want to type this data into
 * MCUINIT in order to reverse engineer the waveforms.
 */

/*
 * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
 * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
 * NOTE that unused areas of the table are used to hold NOP, precharge
 * and mode register set sequences.
 *
 */
#define	UPMA_NOP_ADDR			0x5
#define	UPMA_PRECHARGE_ADDR		0x6
#define UPMA_MRS_ADDR			0x12

#define UPM_SINGLE_READ_ADDR	0x00
#define UPM_BURST_READ_ADDR		0x08
#define UPM_SINGLE_WRITE_ADDR	0x18
#define UPM_BURST_WRITE_ADDR	0x20
#define	UPM_REFRESH_ADDR		0x30

const uint sdram_upm_table[] = {
	/* single read   (offset 0x00 in upm ram) */
	0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
	0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
	/* burst read    (offset 0x08 in upm ram) */
	0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
	0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
	0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
	0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
	/* single write  (offset 0x18 in upm ram) */
	0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* burst write   (offset 0x20 in upm ram) */
	0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
	0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* refresh       (offset 0x30 in upm ram) */
	0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* exception     (offset 0x3C in upm ram) */
};

const uint selectmap_upm_table[] = {
	/* single read   (offset 0x00 in upm ram) */
	0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	/* burst read    (offset 0x08 in upm ram) */
	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* single write  (offset 0x18 in upm ram) */
	0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* burst write   (offset 0x20 in upm ram) */
	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* refresh       (offset 0x30 in upm ram) */
	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* exception     (offset 0x3C in upm ram) */
	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
};

/*
 * Check board identity.  Always successful (gives information only)
 */
int checkboard (void)
{
	char *s;
	char buf[64];
	int i;

	i = getenv_f("board_id", buf, sizeof (buf));
	s = (i > 0) ? buf : NULL;

	if (s) {
		printf ("%s ", s);
	} else {
		printf ("<unknown> ");
	}

	i = getenv_f("serial#", buf, sizeof (buf));
	s = (i > 0) ? buf : NULL;

	if (s) {
		printf ("S/N %s\n", s);
	} else {
		printf ("S/N <unknown>\n");
	}

	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
	return (0);
}

/*
 * Initialize SDRAM
 */
phys_size_t initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	upmconfig (UPMA,
		   (uint *) sdram_upm_table,
		   sizeof (sdram_upm_table) / sizeof (uint)
		);

	/*
	 * Setup MAMR register
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	/*
	 * Map CS1* to SDRAM bank
	 */
	memctl->memc_or1 = CONFIG_SYS_OR1;
	memctl->memc_br1 = CONFIG_SYS_BR1;

	/*
	 * Perform SDRAM initialization sequence:
	 * 1. Apply at least one NOP command
	 * 2. 100 uS delay (JEDEC standard says 200 uS)
	 * 3. Issue 4 precharge commands
	 * 4. Perform two refresh cycles
	 * 5. Program mode register
	 *
	 * Program SDRAM for standard operation, sequential burst, burst length
	 * of 4, CAS latency of 2.
	 */
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (0) | UPMA_NOP_ADDR;
	udelay (200);
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;

	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (2) | UPM_REFRESH_ADDR;

	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (1) | UPMA_MRS_ADDR;

	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (0) | UPMA_NOP_ADDR;
	/*
	 * Enable refresh
	 */
	memctl->memc_mamr |= MAMR_PTAE;

	return (SDRAM_SIZE);
}

/*
 * Disk On Chip (DOC) Millenium initialization.
 * The DOC lives in the CS2* space
 */
#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	printf ("Probing at 0x%.8x: ", DOC_BASE);
	doc_probe (DOC_BASE);
}
#endif

/*
 * Miscellaneous intialization
 */
int misc_init_r (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	/*
	 * Set up UPMB to handle the Virtex FPGA SelectMap interface
	 */
	upmconfig (UPMB, (uint *) selectmap_upm_table,
		   sizeof (selectmap_upm_table) / sizeof (uint));

	memctl->memc_mbmr = 0x0;

	config_mpc8xx_ioports (immr);

#if defined(CONFIG_CMD_MII)
	mii_init ();
#endif

#if defined(CONFIG_FPGA)
	gen860t_init_fpga ();
#endif
	return 0;
}

/*
 * Final init hook before entering command loop.
 */
int last_stage_init (void)
{
#if !defined(CONFIG_SC)
	char buf[256];
	int i;

	/*
	 * Turn the beeper volume all the way down in case this is a warm boot.
	 */
	set_beeper_volume (-64);
	init_beeper ();

	/*
	 * Read the environment to see what to do with the beeper
	 */
	i = getenv_f("beeper", buf, sizeof (buf));
	if (i > 0) {
		do_beeper (buf);
	}
#endif
	return 0;
}

/*
 * Stub to make POST code happy.  Can't self-poweroff, so just hang.
 */
void board_poweroff (void)
{
	puts ("### Please power off the board ###\n");
	while (1);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Keith Outwater, keith_outwater@mvis.com
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	7	*/
	8
	9	#include <virtex2.h>
	10	#include <common.h>
	11	#include <mpc8xx.h>
	12	#include <asm/8xx_immap.h>
	13	#include "beeper.h"
	14	#include "fpga.h"
	15	#include "ioport.h"
	16
d87080b7 WD	17	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	18
c609719b WD	19	#ifdef CONFIG_STATUS_LED
	20	#include <status_led.h>
	21	#endif
	22
77a31854	23	#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
c609719b WD	24	#include <net.h>
	25	#endif
	26
	27	#if 0
	28	#define GEN860T_DEBUG
	29	#endif
	30
	31	#ifdef GEN860T_DEBUG
	32	#define PRINTF(fmt,args...) printf (fmt ,##args)
	33	#else
	34	#define PRINTF(fmt,args...)
	35	#endif
	36
	37	/*
	38	* The following UPM init tables were generated automatically by
	39	* Motorola's MCUINIT program. See the README file for UPM to
	40	* SDRAM pin assignments if you want to type this data into
	41	* MCUINIT in order to reverse engineer the waveforms.
	42	*/
	43
	44	/*
	45	* UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
	46	* (UPMA) and Virtex FPGA SelectMap interface (UPMB).
	47	* NOTE that unused areas of the table are used to hold NOP, precharge
	48	* and mode register set sequences.
	49	*
	50	*/
	51	#define UPMA_NOP_ADDR 0x5
	52	#define UPMA_PRECHARGE_ADDR 0x6
	53	#define UPMA_MRS_ADDR 0x12
	54
	55	#define UPM_SINGLE_READ_ADDR 0x00
	56	#define UPM_BURST_READ_ADDR 0x08
	57	#define UPM_SINGLE_WRITE_ADDR 0x18
	58	#define UPM_BURST_WRITE_ADDR 0x20
	59	#define UPM_REFRESH_ADDR 0x30
	60
	61	const uint sdram_upm_table[] = {
	62	/* single read (offset 0x00 in upm ram) */
	63	0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
	64	0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
	65	/* burst read (offset 0x08 in upm ram) */
	66	0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
	67	0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
	68	0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
	69	0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
	70	/* single write (offset 0x18 in upm ram) */
	71	0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
	72	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	73	/* burst write (offset 0x20 in upm ram) */
	74	0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
	75	0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	76	0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
	77	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	78	/* refresh (offset 0x30 in upm ram) */
	79	0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
	80	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	81	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	82	/* exception (offset 0x3C in upm ram) */
bf9e3b38	83	};
c609719b WD	84
	85	const uint selectmap_upm_table[] = {
	86	/* single read (offset 0x00 in upm ram) */
	87	0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
	88	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	89	/* burst read (offset 0x08 in upm ram) */
	90	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	91	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	92	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	93	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	94	/* single write (offset 0x18 in upm ram) */
	95	0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
	96	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	97	/* burst write (offset 0x20 in upm ram) */
	98	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	99	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	100	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	101	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	102	/* refresh (offset 0x30 in upm ram) */
	103	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	104	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	105	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	106	/* exception (offset 0x3C in upm ram) */
	107	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
	108	};
	109
	110	/*
	111	* Check board identity. Always successful (gives information only)
	112	*/
bf9e3b38	113	int checkboard (void)
c609719b	114	{
77ddac94 WD	115	char *s;
77ddac94 WD	116	char buf[64];
bf9e3b38	117	int i;
c609719b	118
cdb74977	119	i = getenv_f("board_id", buf, sizeof (buf));
bf9e3b38	120	s = (i > 0) ? buf : NULL;
c609719b WD	121
c609719b WD	122	if (s) {
bf9e3b38	123	printf ("%s ", s);
c609719b	124	} else {
bf9e3b38	125	printf ("<unknown> ");
c609719b WD	126	}
c609719b WD	127
cdb74977	128	i = getenv_f("serial#", buf, sizeof (buf));
bf9e3b38	129	s = (i > 0) ? buf : NULL;
c609719b WD	130
c609719b WD	131	if (s) {
bf9e3b38	132	printf ("S/N %s\n", s);
c609719b	133	} else {
bf9e3b38	134	printf ("S/N <unknown>\n");
c609719b WD	135	}
c609719b WD	136
bf9e3b38 WD	137	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
	138	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
	139	return (0);
c609719b WD	140	}
	141
	142	/*
	143	* Initialize SDRAM
	144	*/
9973e3c6	145	phys_size_t initdram (int board_type)
c609719b	146	{
6d0f6bcf	147	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
bf9e3b38 WD	148	volatile memctl8xx_t *memctl = &immr->im_memctl;
	149
	150	upmconfig (UPMA,
	151	(uint *) sdram_upm_table,
	152	sizeof (sdram_upm_table) / sizeof (uint)
	153	);
	154
	155	/*
	156	* Setup MAMR register
	157	*/
6d0f6bcf JCPV	158	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
6d0f6bcf JCPV	159	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
bf9e3b38 WD	160
	161	/*
	162	* Map CS1* to SDRAM bank
	163	*/
6d0f6bcf JCPV	164	memctl->memc_or1 = CONFIG_SYS_OR1;
6d0f6bcf JCPV	165	memctl->memc_br1 = CONFIG_SYS_BR1;
c609719b WD	166
	167	/*
	168	* Perform SDRAM initialization sequence:
	169	* 1. Apply at least one NOP command
	170	* 2. 100 uS delay (JEDEC standard says 200 uS)
	171	* 3. Issue 4 precharge commands
	172	* 4. Perform two refresh cycles
	173	* 5. Program mode register
	174	*
	175	* Program SDRAM for standard operation, sequential burst, burst length
	176	* of 4, CAS latency of 2.
	177	*/
bf9e3b38	178	memctl->memc_mar = 0x00000000;
c609719b	179	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38 WD	180	MCR_MLCF (0) \| UPMA_NOP_ADDR;
	181	udelay (200);
	182	memctl->memc_mar = 0x00000000;
c609719b	183	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	184	MCR_MLCF (4) \| UPMA_PRECHARGE_ADDR;
c609719b	185
bf9e3b38	186	memctl->memc_mar = 0x00000000;
c609719b	187	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	188	MCR_MLCF (2) \| UPM_REFRESH_ADDR;
c609719b	189
bf9e3b38	190	memctl->memc_mar = 0x00000088;
c609719b	191	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	192	MCR_MLCF (1) \| UPMA_MRS_ADDR;
c609719b	193
bf9e3b38	194	memctl->memc_mar = 0x00000000;
c609719b	195	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	196	MCR_MLCF (0) \| UPMA_NOP_ADDR;
c609719b WD	197	/*
	198	* Enable refresh
	199	*/
bf9e3b38	200	memctl->memc_mamr \|= MAMR_PTAE;
c609719b	201
bf9e3b38	202	return (SDRAM_SIZE);
c609719b WD	203	}
	204
	205	/*
	206	* Disk On Chip (DOC) Millenium initialization.
	207	* The DOC lives in the CS2* space
	208	*/
c508a4ce	209	#if defined(CONFIG_CMD_DOC)
bf9e3b38	210	void doc_init (void)
c609719b	211	{
bf9e3b38 WD	212	printf ("Probing at 0x%.8x: ", DOC_BASE);
bf9e3b38 WD	213	doc_probe (DOC_BASE);
c609719b WD	214	}
	215	#endif
	216
	217	/*
	218	* Miscellaneous intialization
	219	*/
bf9e3b38	220	int misc_init_r (void)
c609719b	221	{
6d0f6bcf	222	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
bf9e3b38	223	volatile memctl8xx_t *memctl = &immr->im_memctl;
c609719b WD	224
	225	/*
	226	* Set up UPMB to handle the Virtex FPGA SelectMap interface
	227	*/
bf9e3b38 WD	228	upmconfig (UPMB, (uint *) selectmap_upm_table,
bf9e3b38 WD	229	sizeof (selectmap_upm_table) / sizeof (uint));
c609719b	230
bf9e3b38	231	memctl->memc_mbmr = 0x0;
c609719b	232
bf9e3b38	233	config_mpc8xx_ioports (immr);
c609719b	234
c508a4ce	235	#if defined(CONFIG_CMD_MII)
bf9e3b38	236	mii_init ();
c609719b WD	237	#endif
c609719b WD	238
0133502e	239	#if defined(CONFIG_FPGA)
bf9e3b38	240	gen860t_init_fpga ();
c609719b WD	241	#endif
	242	return 0;
	243	}
	244
	245	/*
	246	* Final init hook before entering command loop.
	247	*/
bf9e3b38	248	int last_stage_init (void)
c609719b	249	{
7aa78614	250	#if !defined(CONFIG_SC)
77ddac94	251	char buf[256];
c609719b WD	252	int i;
	253
	254	/*
7aa78614	255	* Turn the beeper volume all the way down in case this is a warm boot.
c609719b	256	*/
bf9e3b38 WD	257	set_beeper_volume (-64);
bf9e3b38 WD	258	init_beeper ();
c609719b WD	259
	260	/*
	261	* Read the environment to see what to do with the beeper
	262	*/
cdb74977	263	i = getenv_f("beeper", buf, sizeof (buf));
c609719b	264	if (i > 0) {
bf9e3b38	265	do_beeper (buf);
c609719b	266	}
7aa78614	267	#endif
c609719b WD	268	return 0;
c609719b WD	269	}
7aa78614 WD	270
	271	/*
	272	* Stub to make POST code happy. Can't self-poweroff, so just hang.
	273	*/
bf9e3b38	274	void board_poweroff (void)
7aa78614	275	{
bf9e3b38 WD	276	puts ("### Please power off the board ###\n");
bf9e3b38 WD	277	while (1);
7aa78614	278	}