[people/ms/u-boot.git] / board / genesi / mx51_efikamx / efikamx.c

/*
 * Copyright (C) 2009 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 * Copyright (C) 2009-2012 Genesi USA, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx51.h>
#include <asm/gpio.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Compile-time error checking
 */
#ifndef	CONFIG_MXC_SPI
#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
#endif

/*
 * Board revisions
 *
 * Note that we get these revisions here for convenience, but we only set
 * up for the production model Smarttop (1.3) and Smartbook (2.0).
 *
 */
#define	EFIKAMX_BOARD_REV_11	0x1
#define	EFIKAMX_BOARD_REV_12	0x2
#define	EFIKAMX_BOARD_REV_13	0x3
#define	EFIKAMX_BOARD_REV_14	0x4

#define	EFIKASB_BOARD_REV_13	0x1
#define	EFIKASB_BOARD_REV_20	0x2

/*
 * Board identification
 */
static u32 get_mx_rev(void)
{
	u32 rev = 0;
	/*
	 * Retrieve board ID:
	 *
	 *  gpio: 16 17 11
	 *  ==============
	 *	r1.1:  1+ 1  1
	 *	r1.2:  1  1  0
	 *	r1.3:  1  0  1
	 *	r1.4:  1  0  0
	 *
	 * + note: r1.1 does not strap this pin properly so it needs to
	 *         be hacked or ignored.
	 */

	/* set to 1 in order to get correct value on board rev 1.1 */
	gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
	gpio_direction_input(IMX_GPIO_NR(3, 11));
	gpio_direction_input(IMX_GPIO_NR(3, 16));
	gpio_direction_input(IMX_GPIO_NR(3, 17));

	rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
	rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
	rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;

	return (~rev & 0x7) + 1;
}

static iomux_v3_cfg_t const efikasb_revision_pads[] = {
	MX51_PAD_EIM_CS3__GPIO2_28,
	MX51_PAD_EIM_CS4__GPIO2_29,
};

static inline u32 get_sb_rev(void)
{
	u32 rev = 0;

	imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
				ARRAY_SIZE(efikasb_revision_pads));
	gpio_direction_input(IMX_GPIO_NR(2, 28));
	gpio_direction_input(IMX_GPIO_NR(2, 29));

	rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
	rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;

	return rev;
}

inline uint32_t get_efikamx_rev(void)
{
	if (machine_is_efikamx())
		return get_mx_rev();
	else if (machine_is_efikasb())
		return get_sb_rev();
}

u32 get_board_rev(void)
{
	return get_cpu_rev() | (get_efikamx_rev() << 8);
}

/*
 * DRAM initialization
 */
int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
						PHYS_SDRAM_1_SIZE);
	return 0;
}

/*
 * UART configuration
 */
static iomux_v3_cfg_t const efikamx_uart_pads[] = {
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,
};

/*
 * SPI configuration
 */
static iomux_v3_cfg_t const efikamx_spi_pads[] = {
	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	MX51_PAD_CSPI1_SS0__GPIO4_24,
	MX51_PAD_CSPI1_SS1__GPIO4_25,
	MX51_PAD_GPIO1_6__GPIO1_6,
};

#define EFIKAMX_SPI_SS0		IMX_GPIO_NR(4, 24)
#define EFIKAMX_SPI_SS1		IMX_GPIO_NR(4, 25)
#define EFIKAMX_PMIC_IRQ	IMX_GPIO_NR(1, 6)

/*
 * PMIC configuration
 */
#ifdef CONFIG_MXC_SPI
static void power_init(void)
{
	unsigned int val;
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
	struct pmic *p;

	pmic_init();
	p = get_pmic();

	/* Write needed to Power Gate 2 register */
	pmic_reg_read(p, REG_POWER_MISC, &val);
	val &= ~PWGT2SPIEN;
	pmic_reg_write(p, REG_POWER_MISC, val);

	/* Externally powered */
	pmic_reg_read(p, REG_CHARGE, &val);
	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
	pmic_reg_write(p, REG_CHARGE, val);

	/* power up the system first */
	pmic_reg_write(p, REG_POWER_MISC, PWUP);

	/* Set core voltage to 1.1V */
	pmic_reg_read(p, REG_SW_0, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
	pmic_reg_write(p, REG_SW_0, val);

	/* Setup VCC (SW2) to 1.25 */
	pmic_reg_read(p, REG_SW_1, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
	pmic_reg_write(p, REG_SW_1, val);

	/* Setup 1V2_DIG1 (SW3) to 1.25 */
	pmic_reg_read(p, REG_SW_2, &val);
	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
	pmic_reg_write(p, REG_SW_2, val);
	udelay(50);

	/* Raise the core frequency to 800MHz */
	writel(0x0, &mxc_ccm->cacrr);

	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
	/* Setup the switcher mode for SW1 & SW2*/
	pmic_reg_read(p, REG_SW_4, &val);
	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
		(SWMODE_MASK << SWMODE2_SHIFT)));
	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
	pmic_reg_write(p, REG_SW_4, val);

	/* Setup the switcher mode for SW3 & SW4 */
	pmic_reg_read(p, REG_SW_5, &val);
	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
		(SWMODE_MASK << SWMODE4_SHIFT)));
	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
	pmic_reg_write(p, REG_SW_5, val);

	/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
	pmic_reg_read(p, REG_SETTING_0, &val);
	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
	val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
	pmic_reg_write(p, REG_SETTING_0, val);

	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
	pmic_reg_read(p, REG_SETTING_1, &val);
	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
	pmic_reg_write(p, REG_SETTING_1, val);

	/* Enable VGEN1, VGEN2, VDIG, VPLL */
	pmic_reg_read(p, REG_MODE_0, &val);
	val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
	pmic_reg_write(p, REG_MODE_0, val);

	/* Configure VGEN3 and VCAM regulators to use external PNP */
	val = VGEN3CONFIG | VCAMCONFIG;
	pmic_reg_write(p, REG_MODE_1, val);
	udelay(200);

	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
		VVIDEOEN | VAUDIOEN | VSDEN;
	pmic_reg_write(p, REG_MODE_1, val);

	pmic_reg_read(p, REG_POWER_CTL2, &val);
	val |= WDIRESET;
	pmic_reg_write(p, REG_POWER_CTL2, val);

	udelay(2500);
}
#else
static inline void power_init(void) { }
#endif

/*
 * MMC configuration
 */
#ifdef CONFIG_FSL_ESDHC

struct fsl_esdhc_cfg esdhc_cfg[2] = {
	{MMC_SDHC1_BASE_ADDR},
	{MMC_SDHC2_BASE_ADDR},
};

static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
	MX51_PAD_SD1_CMD__SD1_CMD,
	MX51_PAD_SD1_CLK__SD1_CLK,
	MX51_PAD_SD1_DATA0__SD1_DATA0,
	MX51_PAD_SD1_DATA1__SD1_DATA1,
	MX51_PAD_SD1_DATA2__SD1_DATA2,
	MX51_PAD_SD1_DATA3__SD1_DATA3,
	MX51_PAD_GPIO1_1__SD1_WP,
};

#define EFIKAMX_SDHC1_WP	IMX_GPIO_NR(1, 1)

static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
	MX51_PAD_GPIO1_0__SD1_CD,
	MX51_PAD_EIM_CS2__SD1_CD,
};

#define EFIKAMX_SDHC1_CD	IMX_GPIO_NR(1, 0)
#define EFIKASB_SDHC1_CD	IMX_GPIO_NR(2, 27)

static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
	MX51_PAD_SD2_CMD__SD2_CMD,
	MX51_PAD_SD2_CLK__SD2_CLK,
	MX51_PAD_SD2_DATA0__SD2_DATA0,
	MX51_PAD_SD2_DATA1__SD2_DATA1,
	MX51_PAD_SD2_DATA2__SD2_DATA2,
	MX51_PAD_SD2_DATA3__SD2_DATA3,
	MX51_PAD_GPIO1_7__SD2_WP,
	MX51_PAD_GPIO1_8__SD2_CD,
};

#define EFIKASB_SDHC2_CD	IMX_GPIO_NR(1, 8)
#define EFIKASB_SDHC2_WP	IMX_GPIO_NR(1, 7)

static inline uint32_t efikamx_mmc_getcd(u32 base)
{
	if (base == MMC_SDHC1_BASE_ADDR)
		if (machine_is_efikamx())
			return EFIKAMX_SDHC1_CD;
		else
			return EFIKASB_SDHC1_CD;
	else
		return EFIKASB_SDHC2_CD;
}

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
	int ret = !gpio_get_value(cd);

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;

	/*
	 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
	 */
	imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
					ARRAY_SIZE(efikamx_sdhc1_pads));
	gpio_direction_input(EFIKAMX_SDHC1_WP);

	/*
	 * Smartbook and Smarttop differ on the location of eSDHC1
	 * carrier-detect GPIO
	 */
	if (machine_is_efikamx()) {
		imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
		gpio_direction_input(EFIKAMX_SDHC1_CD);
	} else if (machine_is_efikasb()) {
		imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
		gpio_direction_input(EFIKASB_SDHC1_CD);
	}

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);

	if (machine_is_efikasb()) {

		imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
						ARRAY_SIZE(efikasb_sdhc2_pads));
		gpio_direction_input(EFIKASB_SDHC2_CD);
		gpio_direction_input(EFIKASB_SDHC2_WP);
		if (!ret)
			ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
	}

	return ret;
}
#endif

/*
 * PATA
 */
static iomux_v3_cfg_t const efikamx_pata_pads[] = {
	MX51_PAD_NANDF_WE_B__PATA_DIOW,
	MX51_PAD_NANDF_RE_B__PATA_DIOR,
	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
	MX51_PAD_NANDF_CLE__PATA_RESET_B,
	MX51_PAD_NANDF_WP_B__PATA_DMACK,
	MX51_PAD_NANDF_RB0__PATA_DMARQ,
	MX51_PAD_NANDF_RB1__PATA_IORDY,
	MX51_PAD_GPIO_NAND__PATA_INTRQ,
	MX51_PAD_NANDF_CS2__PATA_CS_0,
	MX51_PAD_NANDF_CS3__PATA_CS_1,
	MX51_PAD_NANDF_CS4__PATA_DA_0,
	MX51_PAD_NANDF_CS5__PATA_DA_1,
	MX51_PAD_NANDF_CS6__PATA_DA_2,
	MX51_PAD_NANDF_D15__PATA_DATA15,
	MX51_PAD_NANDF_D14__PATA_DATA14,
	MX51_PAD_NANDF_D13__PATA_DATA13,
	MX51_PAD_NANDF_D12__PATA_DATA12,
	MX51_PAD_NANDF_D11__PATA_DATA11,
	MX51_PAD_NANDF_D10__PATA_DATA10,
	MX51_PAD_NANDF_D9__PATA_DATA9,
	MX51_PAD_NANDF_D8__PATA_DATA8,
	MX51_PAD_NANDF_D7__PATA_DATA7,
	MX51_PAD_NANDF_D6__PATA_DATA6,
	MX51_PAD_NANDF_D5__PATA_DATA5,
	MX51_PAD_NANDF_D4__PATA_DATA4,
	MX51_PAD_NANDF_D3__PATA_DATA3,
	MX51_PAD_NANDF_D2__PATA_DATA2,
	MX51_PAD_NANDF_D1__PATA_DATA1,
	MX51_PAD_NANDF_D0__PATA_DATA0,
};

/*
 * EHCI USB
 */
#ifdef	CONFIG_CMD_USB
extern void setup_iomux_usb(void);
#else
static inline void setup_iomux_usb(void) { }
#endif

/*
 * LED configuration
 *
 * Smarttop LED pad config is done in the DCD
 *
 */
#define EFIKAMX_LED_BLUE	IMX_GPIO_NR(3, 13)
#define EFIKAMX_LED_GREEN	IMX_GPIO_NR(3, 14)
#define EFIKAMX_LED_RED		IMX_GPIO_NR(3, 15)

static iomux_v3_cfg_t const efikasb_led_pads[] = {
	MX51_PAD_GPIO1_3__GPIO1_3,
	MX51_PAD_EIM_CS0__GPIO2_25,
};

#define EFIKASB_CAPSLOCK_LED	IMX_GPIO_NR(2, 25)
#define EFIKASB_MESSAGE_LED	IMX_GPIO_NR(1, 3) /* Note: active low */

/*
 * Board initialization
 */
int board_early_init_f(void)
{
	if (machine_is_efikasb()) {
		imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
						ARRAY_SIZE(efikasb_led_pads));
		gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
		gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
	} else if (machine_is_efikamx()) {
		/*
		 * Set up GPIO directions for LEDs.
		 * IOMUX has been done in the DCD already.
		 * Turn the red LED on for pre-relocation code.
		 */
		gpio_direction_output(EFIKAMX_LED_BLUE, 0);
		gpio_direction_output(EFIKAMX_LED_GREEN, 0);
		gpio_direction_output(EFIKAMX_LED_RED, 1);
	}

	/*
	 * Both these pad configurations for UART and SPI are kind of redundant
	 * since they are the Power-On Defaults for the i.MX51. But, it seems we
	 * should make absolutely sure that they are set up correctly.
	 */
	imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
					ARRAY_SIZE(efikamx_uart_pads));
	imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
					ARRAY_SIZE(efikamx_spi_pads));

	/* not technically required for U-Boot operation but do it anyway. */
	gpio_direction_input(EFIKAMX_PMIC_IRQ);
	/* Deselect both CS for now, otherwise NOR doesn't probe properly. */
	gpio_direction_output(EFIKAMX_SPI_SS0, 0);
	gpio_direction_output(EFIKAMX_SPI_SS1, 1);

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int board_late_init(void)
{
	if (machine_is_efikamx()) {
		/*
		 * Set up Blue LED for "In U-Boot" status.
		 * We're all relocated and ready to U-Boot!
		 */
		gpio_set_value(EFIKAMX_LED_RED, 0);
		gpio_set_value(EFIKAMX_LED_GREEN, 0);
		gpio_set_value(EFIKAMX_LED_BLUE, 1);
	}

	power_init();

	imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
					ARRAY_SIZE(efikamx_pata_pads));
	setup_iomux_usb();

	return 0;
}

int checkboard(void)
{
	u32 rev = get_efikamx_rev();

	printf("Board: Genesi Efika MX ");
	if (machine_is_efikamx())
		printf("Smarttop (1.%i)\n", rev & 0xf);
	else if (machine_is_efikasb())
		printf("Smartbook\n");

	return 0;
}
Commit	Line	Data
d5914017	1	/*
fdd63c93	2	* Copyright (C) 2009 Freescale Semiconductor, Inc.
d5914017	3	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
fdd63c93	4	* Copyright (C) 2009-2012 Genesi USA, Inc.
d5914017 MV	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <asm/io.h>
fdd63c93	27	#include <asm/arch/iomux-mx51.h>
e70a1060	28	#include <asm/gpio.h>
d5914017 MV	29	#include <asm/errno.h>
	30	#include <asm/arch/sys_proto.h>
	31	#include <asm/arch/crm_regs.h>
a2ac1b3a	32	#include <asm/arch/clock.h>
d5914017 MV	33	#include <i2c.h>
	34	#include <mmc.h>
	35	#include <fsl_esdhc.h>
9c38f7df	36	#include <pmic.h>
d5914017 MV	37	#include <fsl_pmic.h>
	38	#include <mc13892.h>
	39
	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	/*
	43	* Compile-time error checking
	44	*/
	45	#ifndef CONFIG_MXC_SPI
	46	#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
	47	#endif
	48
	49	/*
fdd63c93 MS	50	* Board revisions
	51	*
	52	* Note that we get these revisions here for convenience, but we only set
	53	* up for the production model Smarttop (1.3) and Smartbook (2.0).
	54	*
d5914017	55	*/
d5914017 MV	56	#define EFIKAMX_BOARD_REV_11 0x1
	57	#define EFIKAMX_BOARD_REV_12 0x2
	58	#define EFIKAMX_BOARD_REV_13 0x3
	59	#define EFIKAMX_BOARD_REV_14 0x4
	60
af708cba MV	61	#define EFIKASB_BOARD_REV_13 0x1
	62	#define EFIKASB_BOARD_REV_20 0x2
	63
d5914017 MV	64	/*
	65	* Board identification
	66	*/
fdd63c93	67	static u32 get_mx_rev(void)
d5914017 MV	68	{
	69	u32 rev = 0;
	70	/*
	71	* Retrieve board ID:
fdd63c93 MS	72	*
	73	* gpio: 16 17 11
	74	* ==============
	75	* r1.1: 1+ 1 1
	76	* r1.2: 1 1 0
	77	* r1.3: 1 0 1
	78	* r1.4: 1 0 0
	79	*
	80	* + note: r1.1 does not strap this pin properly so it needs to
	81	* be hacked or ignored.
d5914017	82	*/
d5914017	83
fdd63c93	84	/* set to 1 in order to get correct value on board rev 1.1 */
ac966aac SB	85	gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
	86	gpio_direction_input(IMX_GPIO_NR(3, 11));
	87	gpio_direction_input(IMX_GPIO_NR(3, 16));
	88	gpio_direction_input(IMX_GPIO_NR(3, 17));
d5914017	89
ac966aac SB	90	rev \|= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
	91	rev \|= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
	92	rev \|= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
d5914017 MV	93
	94	return (~rev & 0x7) + 1;
	95	}
	96
6e142320	97	static iomux_v3_cfg_t const efikasb_revision_pads[] = {
fdd63c93 MS	98	MX51_PAD_EIM_CS3__GPIO2_28,
	99	MX51_PAD_EIM_CS4__GPIO2_29,
	100	};
	101
	102	static inline u32 get_sb_rev(void)
af708cba MV	103	{
	104	u32 rev = 0;
	105
fdd63c93 MS	106	imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
fdd63c93 MS	107	ARRAY_SIZE(efikasb_revision_pads));
ac966aac SB	108	gpio_direction_input(IMX_GPIO_NR(2, 28));
ac966aac SB	109	gpio_direction_input(IMX_GPIO_NR(2, 29));
af708cba	110
ac966aac SB	111	rev \|= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
ac966aac SB	112	rev \|= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
af708cba MV	113
	114	return rev;
	115	}
	116
fdd63c93	117	inline uint32_t get_efikamx_rev(void)
af708cba MV	118	{
af708cba MV	119	if (machine_is_efikamx())
fdd63c93 MS	120	return get_mx_rev();
	121	else if (machine_is_efikasb())
	122	return get_sb_rev();
af708cba MV	123	}
af708cba MV	124
d5914017 MV	125	u32 get_board_rev(void)
d5914017 MV	126	{
fdd63c93	127	return get_cpu_rev() \| (get_efikamx_rev() << 8);
d5914017 MV	128	}
	129
	130	/*
	131	* DRAM initialization
	132	*/
	133	int dram_init(void)
	134	{
	135	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	136	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
fdd63c93	137	PHYS_SDRAM_1_SIZE);
d5914017 MV	138	return 0;
	139	}
	140
	141	/*
	142	* UART configuration
	143	*/
6e142320	144	static iomux_v3_cfg_t const efikamx_uart_pads[] = {
fdd63c93 MS	145	MX51_PAD_UART1_RXD__UART1_RXD,
	146	MX51_PAD_UART1_TXD__UART1_TXD,
	147	MX51_PAD_UART1_RTS__UART1_RTS,
	148	MX51_PAD_UART1_CTS__UART1_CTS,
	149	};
d5914017 MV	150
	151	/*
	152	* SPI configuration
	153	*/
6e142320	154	static iomux_v3_cfg_t const efikamx_spi_pads[] = {
fdd63c93 MS	155	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	156	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	157	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	158	MX51_PAD_CSPI1_SS0__GPIO4_24,
	159	MX51_PAD_CSPI1_SS1__GPIO4_25,
	160	MX51_PAD_GPIO1_6__GPIO1_6,
	161	};
	162
ac966aac SB	163	#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
	164	#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
	165	#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
d5914017 MV	166
	167	/*
	168	* PMIC configuration
	169	*/
	170	#ifdef CONFIG_MXC_SPI
	171	static void power_init(void)
	172	{
	173	unsigned int val;
	174	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
9c38f7df SB	175	struct pmic *p;
	176
	177	pmic_init();
	178	p = get_pmic();
d5914017 MV	179
d5914017 MV	180	/* Write needed to Power Gate 2 register */
9c38f7df	181	pmic_reg_read(p, REG_POWER_MISC, &val);
d5914017	182	val &= ~PWGT2SPIEN;
9c38f7df	183	pmic_reg_write(p, REG_POWER_MISC, val);
d5914017 MV	184
d5914017 MV	185	/* Externally powered */
9c38f7df	186	pmic_reg_read(p, REG_CHARGE, &val);
d5914017	187	val \|= ICHRG0 \| ICHRG1 \| ICHRG2 \| ICHRG3 \| CHGAUTOB;
9c38f7df	188	pmic_reg_write(p, REG_CHARGE, val);
d5914017 MV	189
d5914017 MV	190	/* power up the system first */
9c38f7df	191	pmic_reg_write(p, REG_POWER_MISC, PWUP);
d5914017 MV	192
d5914017 MV	193	/* Set core voltage to 1.1V */
9c38f7df	194	pmic_reg_read(p, REG_SW_0, &val);
fdd63c93	195	val = (val & ~SWx_VOLT_MASK) \| SWx_1_100V;
9c38f7df	196	pmic_reg_write(p, REG_SW_0, val);
d5914017 MV	197
d5914017 MV	198	/* Setup VCC (SW2) to 1.25 */
9c38f7df	199	pmic_reg_read(p, REG_SW_1, &val);
d5914017	200	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
9c38f7df	201	pmic_reg_write(p, REG_SW_1, val);
d5914017 MV	202
d5914017 MV	203	/* Setup 1V2_DIG1 (SW3) to 1.25 */
9c38f7df	204	pmic_reg_read(p, REG_SW_2, &val);
d5914017	205	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
9c38f7df	206	pmic_reg_write(p, REG_SW_2, val);
d5914017 MV	207	udelay(50);
	208
	209	/* Raise the core frequency to 800MHz */
	210	writel(0x0, &mxc_ccm->cacrr);
	211
	212	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
	213	/* Setup the switcher mode for SW1 & SW2*/
9c38f7df	214	pmic_reg_read(p, REG_SW_4, &val);
d5914017 MV	215	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) \|
	216	(SWMODE_MASK << SWMODE2_SHIFT)));
	217	val \|= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) \|
	218	(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
9c38f7df	219	pmic_reg_write(p, REG_SW_4, val);
d5914017 MV	220
d5914017 MV	221	/* Setup the switcher mode for SW3 & SW4 */
9c38f7df	222	pmic_reg_read(p, REG_SW_5, &val);
d5914017 MV	223	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) \|
	224	(SWMODE_MASK << SWMODE4_SHIFT)));
	225	val \|= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) \|
	226	(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
9c38f7df	227	pmic_reg_write(p, REG_SW_5, val);
d5914017	228
55723954	229	/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
9c38f7df	230	pmic_reg_read(p, REG_SETTING_0, &val);
d5914017	231	val &= ~(VCAM_MASK \| VGEN3_MASK \| VDIG_MASK);
55723954	232	val \|= VDIG_1_8 \| VGEN3_1_8 \| VCAM_2_6;
9c38f7df	233	pmic_reg_write(p, REG_SETTING_0, val);
d5914017 MV	234
d5914017 MV	235	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
9c38f7df	236	pmic_reg_read(p, REG_SETTING_1, &val);
d5914017	237	val &= ~(VVIDEO_MASK \| VSD_MASK \| VAUDIO_MASK);
55723954	238	val \|= VSD_3_15 \| VAUDIO_3_0 \| VVIDEO_2_775 \| VGEN1_1_2 \| VGEN2_3_15;
9c38f7df	239	pmic_reg_write(p, REG_SETTING_1, val);
d5914017	240
55723954 MV	241	/* Enable VGEN1, VGEN2, VDIG, VPLL */
	242	pmic_reg_read(p, REG_MODE_0, &val);
	243	val \|= VGEN1EN \| VDIGEN \| VGEN2EN \| VPLLEN;
	244	pmic_reg_write(p, REG_MODE_0, val);
	245
d5914017 MV	246	/* Configure VGEN3 and VCAM regulators to use external PNP */
d5914017 MV	247	val = VGEN3CONFIG \| VCAMCONFIG;
9c38f7df	248	pmic_reg_write(p, REG_MODE_1, val);
d5914017 MV	249	udelay(200);
	250
	251	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
	252	val = VGEN3EN \| VGEN3CONFIG \| VCAMEN \| VCAMCONFIG \|
55723954	253	VVIDEOEN \| VAUDIOEN \| VSDEN;
9c38f7df	254	pmic_reg_write(p, REG_MODE_1, val);
d5914017	255
9c38f7df	256	pmic_reg_read(p, REG_POWER_CTL2, &val);
d5914017	257	val \|= WDIRESET;
9c38f7df	258	pmic_reg_write(p, REG_POWER_CTL2, val);
d5914017 MV	259
	260	udelay(2500);
	261	}
	262	#else
	263	static inline void power_init(void) { }
	264	#endif
	265
	266	/*
	267	* MMC configuration
	268	*/
	269	#ifdef CONFIG_FSL_ESDHC
fdd63c93	270
d5914017	271	struct fsl_esdhc_cfg esdhc_cfg[2] = {
16e43f35 BT	272	{MMC_SDHC1_BASE_ADDR},
16e43f35 BT	273	{MMC_SDHC2_BASE_ADDR},
d5914017 MV	274	};
d5914017 MV	275
6e142320	276	static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
fdd63c93 MS	277	MX51_PAD_SD1_CMD__SD1_CMD,
	278	MX51_PAD_SD1_CLK__SD1_CLK,
	279	MX51_PAD_SD1_DATA0__SD1_DATA0,
	280	MX51_PAD_SD1_DATA1__SD1_DATA1,
	281	MX51_PAD_SD1_DATA2__SD1_DATA2,
	282	MX51_PAD_SD1_DATA3__SD1_DATA3,
	283	MX51_PAD_GPIO1_1__SD1_WP,
	284	};
	285
ac966aac	286	#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
fdd63c93	287
6e142320	288	static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
fdd63c93 MS	289	MX51_PAD_GPIO1_0__SD1_CD,
	290	MX51_PAD_EIM_CS2__SD1_CD,
	291	};
	292
ac966aac SB	293	#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
ac966aac SB	294	#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
fdd63c93	295
6e142320	296	static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
fdd63c93 MS	297	MX51_PAD_SD2_CMD__SD2_CMD,
	298	MX51_PAD_SD2_CLK__SD2_CLK,
	299	MX51_PAD_SD2_DATA0__SD2_DATA0,
	300	MX51_PAD_SD2_DATA1__SD2_DATA1,
	301	MX51_PAD_SD2_DATA2__SD2_DATA2,
	302	MX51_PAD_SD2_DATA3__SD2_DATA3,
	303	MX51_PAD_GPIO1_7__SD2_WP,
	304	MX51_PAD_GPIO1_8__SD2_CD,
	305	};
	306
ac966aac SB	307	#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
ac966aac SB	308	#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
fdd63c93 MS	309
fdd63c93 MS	310	static inline uint32_t efikamx_mmc_getcd(u32 base)
af708cba	311	{
fdd63c93 MS	312	if (base == MMC_SDHC1_BASE_ADDR)
	313	if (machine_is_efikamx())
	314	return EFIKAMX_SDHC1_CD;
	315	else
	316	return EFIKASB_SDHC1_CD;
af708cba	317	else
fdd63c93	318	return EFIKASB_SDHC2_CD;
af708cba MV	319	}
af708cba MV	320
314284b1	321	int board_mmc_getcd(struct mmc *mmc)
d5914017 MV	322	{
d5914017 MV	323	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
fdd63c93 MS	324	uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
fdd63c93 MS	325	int ret = !gpio_get_value(cd);
d5914017	326
314284b1	327	return ret;
d5914017	328	}
af708cba	329
d5914017 MV	330	int board_mmc_init(bd_t *bis)
	331	{
	332	int ret;
fdd63c93 MS	333
	334	/*
	335	* All Efika MX boards use eSDHC1 with a common write-protect GPIO
	336	*/
	337	imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
	338	ARRAY_SIZE(efikamx_sdhc1_pads));
	339	gpio_direction_input(EFIKAMX_SDHC1_WP);
	340
	341	/*
	342	* Smartbook and Smarttop differ on the location of eSDHC1
	343	* carrier-detect GPIO
	344	*/
	345	if (machine_is_efikamx()) {
	346	imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
	347	gpio_direction_input(EFIKAMX_SDHC1_CD);
	348	} else if (machine_is_efikasb()) {
	349	imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
	350	gpio_direction_input(EFIKASB_SDHC1_CD);
	351	}
	352
a2ac1b3a BT	353	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	354	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	355
fdd63c93 MS	356	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
	357
	358	if (machine_is_efikasb()) {
	359
	360	imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
	361	ARRAY_SIZE(efikasb_sdhc2_pads));
	362	gpio_direction_input(EFIKASB_SDHC2_CD);
	363	gpio_direction_input(EFIKASB_SDHC2_WP);
d5914017 MV	364	if (!ret)
d5914017 MV	365	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
d5914017	366	}
af708cba	367
d5914017 MV	368	return ret;
	369	}
	370	#endif
	371
	372	/*
fdd63c93	373	* PATA
d5914017	374	*/
6e142320	375	static iomux_v3_cfg_t const efikamx_pata_pads[] = {
fdd63c93 MS	376	MX51_PAD_NANDF_WE_B__PATA_DIOW,
	377	MX51_PAD_NANDF_RE_B__PATA_DIOR,
	378	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
	379	MX51_PAD_NANDF_CLE__PATA_RESET_B,
	380	MX51_PAD_NANDF_WP_B__PATA_DMACK,
	381	MX51_PAD_NANDF_RB0__PATA_DMARQ,
	382	MX51_PAD_NANDF_RB1__PATA_IORDY,
	383	MX51_PAD_GPIO_NAND__PATA_INTRQ,
	384	MX51_PAD_NANDF_CS2__PATA_CS_0,
	385	MX51_PAD_NANDF_CS3__PATA_CS_1,
	386	MX51_PAD_NANDF_CS4__PATA_DA_0,
	387	MX51_PAD_NANDF_CS5__PATA_DA_1,
	388	MX51_PAD_NANDF_CS6__PATA_DA_2,
	389	MX51_PAD_NANDF_D15__PATA_DATA15,
	390	MX51_PAD_NANDF_D14__PATA_DATA14,
	391	MX51_PAD_NANDF_D13__PATA_DATA13,
	392	MX51_PAD_NANDF_D12__PATA_DATA12,
	393	MX51_PAD_NANDF_D11__PATA_DATA11,
	394	MX51_PAD_NANDF_D10__PATA_DATA10,
	395	MX51_PAD_NANDF_D9__PATA_DATA9,
	396	MX51_PAD_NANDF_D8__PATA_DATA8,
	397	MX51_PAD_NANDF_D7__PATA_DATA7,
	398	MX51_PAD_NANDF_D6__PATA_DATA6,
	399	MX51_PAD_NANDF_D5__PATA_DATA5,
	400	MX51_PAD_NANDF_D4__PATA_DATA4,
	401	MX51_PAD_NANDF_D3__PATA_DATA3,
	402	MX51_PAD_NANDF_D2__PATA_DATA2,
	403	MX51_PAD_NANDF_D1__PATA_DATA1,
	404	MX51_PAD_NANDF_D0__PATA_DATA0,
	405	};
d5914017	406
d98d8bc1 MV	407	/*
	408	* EHCI USB
	409	*/
	410	#ifdef CONFIG_CMD_USB
	411	extern void setup_iomux_usb(void);
	412	#else
	413	static inline void setup_iomux_usb(void) { }
	414	#endif
	415
d5914017 MV	416	/*
d5914017 MV	417	* LED configuration
fdd63c93 MS	418	*
	419	* Smarttop LED pad config is done in the DCD
	420	*
d5914017	421	*/
ac966aac SB	422	#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
	423	#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
	424	#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
d5914017	425
6e142320	426	static iomux_v3_cfg_t const efikasb_led_pads[] = {
fdd63c93 MS	427	MX51_PAD_GPIO1_3__GPIO1_3,
	428	MX51_PAD_EIM_CS0__GPIO2_25,
	429	};
	430
ac966aac SB	431	#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
ac966aac SB	432	#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
d5914017 MV	433
	434	/*
	435	* Board initialization
	436	*/
d5914017 MV	437	int board_early_init_f(void)
d5914017 MV	438	{
fdd63c93 MS	439	if (machine_is_efikasb()) {
	440	imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
	441	ARRAY_SIZE(efikasb_led_pads));
	442	gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
	443	gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
	444	} else if (machine_is_efikamx()) {
	445	/*
	446	* Set up GPIO directions for LEDs.
	447	* IOMUX has been done in the DCD already.
	448	* Turn the red LED on for pre-relocation code.
	449	*/
	450	gpio_direction_output(EFIKAMX_LED_BLUE, 0);
	451	gpio_direction_output(EFIKAMX_LED_GREEN, 0);
	452	gpio_direction_output(EFIKAMX_LED_RED, 1);
	453	}
	454
	455	/*
	456	* Both these pad configurations for UART and SPI are kind of redundant
	457	* since they are the Power-On Defaults for the i.MX51. But, it seems we
	458	* should make absolutely sure that they are set up correctly.
	459	*/
	460	imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
	461	ARRAY_SIZE(efikamx_uart_pads));
	462	imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
	463	ARRAY_SIZE(efikamx_spi_pads));
	464
	465	/* not technically required for U-Boot operation but do it anyway. */
	466	gpio_direction_input(EFIKAMX_PMIC_IRQ);
	467	/* Deselect both CS for now, otherwise NOR doesn't probe properly. */
	468	gpio_direction_output(EFIKAMX_SPI_SS0, 0);
	469	gpio_direction_output(EFIKAMX_SPI_SS1, 1);
d5914017 MV	470
	471	return 0;
	472	}
	473
	474	int board_init(void)
	475	{
d5914017 MV	476	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	477
	478	return 0;
	479	}
	480
	481	int board_late_init(void)
	482	{
fdd63c93 MS	483	if (machine_is_efikamx()) {
	484	/*
	485	* Set up Blue LED for "In U-Boot" status.
	486	* We're all relocated and ready to U-Boot!
	487	*/
	488	gpio_set_value(EFIKAMX_LED_RED, 0);
	489	gpio_set_value(EFIKAMX_LED_GREEN, 0);
	490	gpio_set_value(EFIKAMX_LED_BLUE, 1);
	491	}
d5914017 MV	492
	493	power_init();
	494
fdd63c93 MS	495	imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
fdd63c93 MS	496	ARRAY_SIZE(efikamx_pata_pads));
d98d8bc1 MV	497	setup_iomux_usb();
d98d8bc1 MV	498
d5914017 MV	499	return 0;
	500	}
	501
	502	int checkboard(void)
	503	{
fdd63c93	504	u32 rev = get_efikamx_rev();
af708cba	505
fdd63c93 MS	506	printf("Board: Genesi Efika MX ");
	507	if (machine_is_efikamx())
	508	printf("Smarttop (1.%i)\n", rev & 0xf);
	509	else if (machine_is_efikasb())
	510	printf("Smartbook\n");
d5914017 MV	511
	512	return 0;
	513	}